lewiz-support / LMAC_CORE2
LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
☆32Updated last year
Related projects ⓘ
Alternatives and complementary repositories for LMAC_CORE2
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆41Updated 3 years ago
- PCI Express controller model☆46Updated 2 years ago
- Verilog PCI express components☆18Updated last year
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆38Updated 5 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆61Updated 7 years ago
- Virtio implementation in SystemVerilog☆46Updated 6 years ago
- Open source FPGA-based NIC and platform for in-network compute☆58Updated 3 weeks ago
- Ethernet switch implementation written in Verilog☆40Updated last year
- Extensible FPGA control platform☆54Updated last year
- Verilog Ethernet components for FPGA implementation☆14Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark☆45Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- ☆24Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆40Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago
- pcie-bench code for NetFPGA/VCU709 cards☆33Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- PCIe (1.0a to 2.0) Virtual host model for verilog☆84Updated last month
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Verilog Content Addressable Memory Module☆102Updated 2 years ago
- SoCRocket - Core Repository☆33Updated 7 years ago
- ☆47Updated 2 years ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆27Updated 11 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆16Updated 5 years ago