Alternatives and similar repositories for LMAC_CORE2

Users that are interested in LMAC_CORE2 are comparing it to the libraries listed below

• lewiz-support / LMAC_CORE1

  View on GitHub
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆19Apr 3, 2023Updated 2 years ago
• adki / cosim_bfm_library

  View on GitHub
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Dec 24, 2024Updated last year
• Xilinx / libsystemctlm-soc

  View on GitHub
  SystemC/TLM-2.0 Co-simulation framework
  ☆268May 21, 2025Updated 8 months ago
• Xilinx / systemctlm-cosim-demo

  View on GitHub
  QEMU libsystemctlm-soc co-simulation demos.
  ☆159May 21, 2025Updated 8 months ago
• hossamfadeel / Verilog-Based-NoC-Simulator

  View on GitHub
  Verilog-Based-NoC-Simulator
  ☆10May 4, 2016Updated 9 years ago
• YosysHQ / sby-gui

  View on GitHub
  GUI for SymbiYosys
  ☆17Oct 13, 2025Updated 4 months ago
• RSPwFPGAs / qemu-hdl-cosim

  View on GitHub
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆52Jan 19, 2021Updated 5 years ago
• verilog-to-routing / libsdcparse

  View on GitHub
  ☆12Feb 6, 2026Updated last week
• twisterss / hardware-traffic-generator

  View on GitHub
  10 Gbit/s flexible and extensible Ethernet FPGA-based traffic generator
  ☆11Oct 3, 2014Updated 11 years ago
• opencomputeproject / ODSA-CDXML

  View on GitHub
  TBD
  ☆14Feb 6, 2025Updated last year
• opensmartnic / panic_with_cocotb

  View on GitHub
  ☆14May 15, 2023Updated 2 years ago
• muneebullashariff / pulpino_soc_uvm_testbench

  View on GitHub
  UVM testbench for verifying the Pulpino SoC
  ☆13Mar 23, 2020Updated 5 years ago
• cornell-brg / pymtl-tutorial-isca2019

  View on GitHub
  Code for PyMTL Tutorial @ ISCA 2019
  ☆11Jun 22, 2019Updated 6 years ago
• growly / bfg

  View on GitHub
  An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
  ☆14Updated this week
• explcre / 21Summer-VE370-Intro-to-Computer-Organization-Projects

  View on GitHub
  21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…
  ☆14Apr 11, 2023Updated 2 years ago
• carlos-jenkins / csv2vcd

  View on GitHub
  Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.
  ☆11Aug 13, 2021Updated 4 years ago
• zetalog / sdfirm

  View on GitHub
  Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.
  ☆20Aug 5, 2025Updated 6 months ago
• cornell-brg / lizard

  View on GitHub
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Jul 29, 2019Updated 6 years ago
• aolofsson / IDEA

  View on GitHub
  ☆33Jan 24, 2020Updated 6 years ago
• bluespec / AWSteria_Infra

  View on GitHub
  "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
  ☆19Sep 26, 2024Updated last year
• Vlsir / Hdl21Schematics

  View on GitHub
  Hdl21 Schematics
  ☆17Jan 24, 2024Updated 2 years ago
• shalan / Chameleon_SoC

  View on GitHub
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆13Mar 28, 2025Updated 10 months ago
• ckchengucsd / ILP-SAT-Detailed-Router

  View on GitHub
  ILP SAT Detailed Router
  ☆13Apr 14, 2020Updated 5 years ago
• Xilinx / pcie-model

  View on GitHub
  PCI Express controller model
  ☆71Oct 5, 2022Updated 3 years ago
• sgherbst / anasymod

  View on GitHub
  A framework for FPGA emulation of mixed-signal systems
  ☆39Jul 28, 2021Updated 4 years ago
• lfd / XtratuM

  View on GitHub
  XtratuM Mirror
  ☆21Apr 7, 2017Updated 8 years ago
• edgarigl / qemu-etrace

  View on GitHub
  Qemu Etrace
  ☆15May 21, 2024Updated last year
• nosnhojn / uvm-utest

  View on GitHub
  ☆19Jun 30, 2015Updated 10 years ago
• preshing / ConsumeDemo

  View on GitHub
  ☆17Jul 9, 2014Updated 11 years ago
• rick-heig / zynq7-cosim

  View on GitHub
  ☆15May 29, 2020Updated 5 years ago
• altera-opensource / ghrd-socfpga

  View on GitHub
  ☆33Mar 19, 2025Updated 10 months ago
• lewiz-support / LMAC_CORE3

  View on GitHub
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Apr 3, 2023Updated 2 years ago
• magical-eda / MAGICAL-CIRCUITS

  View on GitHub
  Circuit release of the MAGICAL project
  ☆40Jan 10, 2020Updated 6 years ago
• forconesi / nfmac10g

  View on GitHub
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆72Jan 29, 2017Updated 9 years ago
• watz0n / arty_xjtag

  View on GitHub
  Xilinx JTAG Toolchain on Digilent Arty board
  ☆17Mar 15, 2018Updated 7 years ago
• aolofsson / POSH

  View on GitHub
  ☆44Jan 26, 2020Updated 6 years ago
• isclouder / microv

  View on GitHub
  kvm hypervisor
  ☆16Dec 20, 2022Updated 3 years ago
• RSPwFPGAs / opae-xilinx

  View on GitHub
  OPAE porting to Xilinx FPGA devices.
  ☆39Aug 5, 2020Updated 5 years ago
• sgherbst / msdsl

  View on GitHub
  Automatic generation of real number models from analog circuits
  ☆48Apr 2, 2024Updated last year