Alternatives and similar repositories for sargraph

Users that are interested in sargraph are comparing it to the libraries listed below

• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated last year
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆31Updated 2 months ago
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆21Updated this week
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated 2 weeks ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆60Updated last year
• Risto97 / PeakRDL-halcpp
  C++ 17 Hardware abstraction layer generator from systemrdl
  ☆12Updated 9 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• vmunoz82 / sudoku-challenge
  Solving Sudokus using open source formal verification tools
  ☆16Updated 2 years ago
• gnuradio / gr-verilog
  ☆17Updated 2 years ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆38Updated 6 months ago
• antmicro / renode-test-action
  GitHub Action allowing to run tests in the Renode framework
  ☆18Updated last week
• SystemRDL / PeakRDL-cheader
  ☆11Updated last month
• antmicro / renode-linux-runner-action
  Run your tests in a configurable, emulated Linux environment with a custom kernel and access to virtual peripherals
  ☆12Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• antmicro / tuttest
  A simple Python utility for extracting documentation snippets from tutorials.
  ☆14Updated last year
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆34Updated 7 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆103Updated last week
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆38Updated last week
• efabless / raptor
  Arm Cortex-M0 based Customizable SoC for IoT Applications
  ☆14Updated 4 years ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆35Updated 3 years ago
• newaetech / sonata-pcb
  Design files and associated documentation for Sonata PCB, part of the Sunburst Project
  ☆17Updated 2 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• psychogenic / microcotb
  micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
  ☆13Updated 3 months ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆63Updated 2 weeks ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆27Updated 5 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago