CMU-SAFARI / CROWLinks
Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA 2019 paper "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability". Paper is at: https://people.inf.ethz.ch/omutlu/pub/CROW-DRAM-substrate-for-performance-energy-reliabil…
☆15Updated 6 years ago
Alternatives and similar repositories for CROW
Users that are interested in CROW are comparing it to the libraries listed below
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- ☆25Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆20Updated 7 years ago
- ☆17Updated 2 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆20Updated last year
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Updated 5 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- ☆40Updated 8 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Tutorial Material from the SST Team☆25Updated 4 months ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Updated 7 years ago
- ☆36Updated 4 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 11 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- ☆13Updated 3 years ago
- ☆14Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago