OpenPOWERFoundation / a2oLinks
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
☆53Updated 8 months ago
Alternatives and similar repositories for a2o
Users that are interested in a2o are comparing it to the libraries listed below
Sorting:
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆49Updated 3 years ago
- OpenSPARC-based SoC☆75Updated 11 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆113Updated 2 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆76Updated 2 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated this week
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- IRSIM switch-level simulator for digital circuits☆35Updated 2 months ago
- Experiments with fixed function renderers and Chisel HDL☆60Updated 6 years ago
- ☆33Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- An open-source custom cache generator.☆34Updated last year
- A pipelined RISC-V processor☆63Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated last month
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- ☆24Updated 4 years ago
- ☆144Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- OpenRISC processor IP core based on Tomasulo algorithm☆35Updated 3 years ago
- Exploring gate level simulation☆58Updated 9 months ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- Mutation Cover with Yosys (MCY)☆90Updated 3 weeks ago
- Simple runtime for Pulp platforms☆50Updated this week