OpenPOWERFoundation / a2oLinks
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
☆48Updated last month
Alternatives and similar repositories for a2o
Users that are interested in a2o are comparing it to the libraries listed below
Sorting:
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆44Updated 2 years ago
- OpenSPARC-based SoC☆69Updated 10 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆109Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- IRSIM switch-level simulator for digital circuits☆34Updated 3 months ago
- 64-bit multicore Linux-capable RISC-V processor☆93Updated 2 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated 3 weeks ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆69Updated last year
- ☆33Updated 2 years ago
- Simple runtime for Pulp platforms☆48Updated last month
- ☆21Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆109Updated last month
- ☆140Updated 3 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- ☆25Updated 4 months ago
- An open-source custom cache generator.☆34Updated last year
- OpenRISC processor IP core based on Tomasulo algorithm☆32Updated 3 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆74Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆62Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆53Updated 4 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆25Updated last month
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated last month