OpenPOWERFoundation / a2oLinks
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
☆50Updated 5 months ago
Alternatives and similar repositories for a2o
Users that are interested in a2o are comparing it to the libraries listed below
Sorting:
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆47Updated 3 years ago
- OpenSPARC-based SoC☆72Updated 11 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆111Updated 2 years ago
- ☆33Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- ☆50Updated last month
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Bitstream relocation and manipulation tool.☆49Updated 2 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- ☆140Updated 3 years ago
- OpenGL 1.x implementation for FPGAs☆105Updated last week
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- ☆22Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆33Updated 3 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 5 months ago
- An implementation of RISC-V☆43Updated last month
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago