fatestudio / RSA4096_NEWLinks
☆13Updated 10 years ago
Alternatives and similar repositories for RSA4096_NEW
Users that are interested in RSA4096_NEW are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆21Updated 11 months ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆32Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- ☆30Updated 2 weeks ago
- ☆29Updated 5 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆28Updated last month
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆45Updated 5 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- ☆27Updated 5 years ago
- ☆12Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆35Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆34Updated 7 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Open-Channel Open-Way Flash Controller☆17Updated 3 years ago
- ☆16Updated 6 years ago
- APB Logic☆19Updated this week
- The memory model was leveraged from micron.☆22Updated 7 years ago