Alternatives and similar repositories for RSA4096_NEW:

Users that are interested in RSA4096_NEW are comparing it to the libraries listed below

• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• raymondrc / riscv-isa-extension-for-SM4
  RISC-V instruction set extensions for SM4 block cipher
  ☆19Updated 4 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• Rajandeep / RSA-CRYPTOSYSTEM-using-verilog
  ☆10Updated 8 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• donpromax / ECC-Verilog-HDL-AutoGenerator
  a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
  ☆11Updated 5 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 6 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆33Updated last month
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆29Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 3 weeks ago
• HeerAmbavi / RSAonVerilog
  Implementation of RSA algorithm on FPGA using Verilog
  ☆26Updated 6 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆11Updated 3 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆17Updated 5 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆27Updated last month
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆43Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆50Updated this week
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆29Updated last year
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago