Alternatives and similar repositories for RSA4096_NEW

Users that are interested in RSA4096_NEW are comparing it to the libraries listed below

• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆28Updated 4 years ago
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 3 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆19Updated 9 months ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• donpromax / ECC-Verilog-HDL-AutoGenerator
  a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
  ☆11Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated 2 weeks ago
• spike556 / HuffmanCode
  hardware implement of huffman coding(written in verilog)
  ☆12Updated 7 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆40Updated 3 weeks ago
• Rajandeep / RSA-CRYPTOSYSTEM-using-verilog
  ☆12Updated 8 years ago
• kinap / AES-Processor
  AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…
  ☆16Updated 8 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated 2 weeks ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆45Updated 5 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆17Updated 5 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆19Updated 11 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆21Updated 4 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆31Updated last year