Alternatives and similar repositories for RSA4096_NEW:

Users that are interested in RSA4096_NEW are comparing it to the libraries listed below

• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 3 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆45Updated 5 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• donpromax / ECC-Verilog-HDL-AutoGenerator
  a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
  ☆11Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• gauravtewari / python-to-verilog
  Generate a Verilog Source file and testbench file for a given Moore FSM
  ☆17Updated 12 years ago
• kinap / AES-Processor
  AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…
  ☆16Updated 8 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• Rajandeep / RSA-CRYPTOSYSTEM-using-verilog
  ☆12Updated 8 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆30Updated this week
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆14Updated 5 years ago
• HeerAmbavi / RSAonVerilog
  Implementation of RSA algorithm on FPGA using Verilog
  ☆28Updated 6 years ago
• Csuk0914 / dnn-rtl
  Verilog RTL Implementation of DNN
  ☆10Updated 6 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆13Updated 2 weeks ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 3 months ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆26Updated 3 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆15Updated 4 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆29Updated last week
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 4 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago