The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
☆38Jun 21, 2023Updated 3 years ago
Alternatives and similar repositories for paranut
Users that are interested in paranut are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆16Jun 29, 2026Updated 2 months ago
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated last year
- A modeling library with virtual components for SystemC and TLM simulators☆203Updated this week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated last month
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆139Sep 5, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆15Apr 28, 2026Updated 4 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆36May 17, 2026Updated 4 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆45Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆319Aug 31, 2026Updated 3 weeks ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆24Aug 10, 2018Updated 8 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 7 years ago
- Algorithmic C Machine Learning Library☆29Sep 10, 2026Updated last week
- A tiny 3-stage RISC-V core written in Chisel.☆18Apr 14, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Linux capable RISC-V SoC designed to be readable and useful.☆164Dec 19, 2025Updated 9 months ago
- Cycle Accurate Network-on-Chip Simulator☆38Jul 11, 2026Updated 2 months ago
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆49Jul 30, 2026Updated last month
- Virtual Platform for NVDLA☆169Aug 23, 2018Updated 8 years ago
- Signal/Image processing techniques applied to subsurface data☆15May 8, 2021Updated 5 years ago
- MatchLib Connections Toolkit - example designs leveraging Connections☆16Sep 10, 2026Updated last week
- ☆158Oct 6, 2023Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Aug 18, 2026Updated last month
- RISC-V SystemC-TLM simulator☆361Feb 20, 2026Updated 7 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆13Jun 9, 2022Updated 4 years ago
- RISC-V Virtual Prototype☆194Jul 21, 2026Updated 2 months ago
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- ☆16May 9, 2022Updated 4 years ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 12 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆58May 16, 2025Updated last year
- Sail RISC-V model☆12Jun 23, 2025Updated last year
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆18Jun 13, 2025Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆401Sep 7, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆15Jan 30, 2024Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆78Dec 29, 2025Updated 8 months ago
- A powerful and modern open-source architecture description language.☆49Oct 18, 2017Updated 8 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆29Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆91Apr 13, 2026Updated 5 months ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Aug 9, 2026Updated last month
- ☆29Nov 5, 2021Updated 4 years ago