hsa-ees / paranutLinks
The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
☆35Updated 2 years ago
Alternatives and similar repositories for paranut
Users that are interested in paranut are comparing it to the libraries listed below
Sorting:
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated last week
- ☆30Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- ☆15Updated 2 weeks ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- ☆65Updated last week
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- PCI Express controller model☆57Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISC-V IOMMU in verilog☆17Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ☆29Updated 4 years ago
- Platform Level Interrupt Controller☆41Updated last year
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- ☆59Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last month
- RISC-V Virtual Prototype☆43Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 7 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago