Alternatives and similar repositories for gan-hls

Users that are interested in gan-hls are comparing it to the libraries listed below

• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• nimish15shah / DPU_DAG_Processing_Unit
  RTL code for the DPU chip designed for irregular graphs
  ☆13Updated 3 years ago
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆16Updated 5 years ago
• racosa / cnn-accelerator
  A Convolutional Neural Network (CNN) hardware accelerator for image recognition
  ☆14Updated 6 years ago
• Charmve / AccANN
  🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
  ☆21Updated last year
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆16Updated 2 years ago
• AILearnerLi / DAC-SDC-2020-SEUer
  ☆26Updated 2 years ago
• jgoeders / dac_sdc_2022_designs
  ☆17Updated 2 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆20Updated 4 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
  2020 xilinx summer school
  ☆18Updated 5 years ago
• fffasttime / AnyPackingNet
  ☆30Updated 7 months ago
• Jiawei888 / FPGA-CNN-Accelerator
  The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…
  ☆11Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆46Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• haroonrl / DNN_HLS_Accelerator
  This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
  ☆10Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆48Updated 5 years ago
• AiArtisan / dac_sdc_2022_champion
  ☆21Updated 3 years ago
• Kareem-Emad / DCNN-Accelerator
  Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
  ☆13Updated 6 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• vrishbhan / Matrix-Multiplication
  Design for 4 x 4 Matrix Multiplication using Verilog
  ☆34Updated 10 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆15Updated 3 years ago
• gkrislara / Image-super-resolution-FPGA
  Deployment of Deep learning Image Super-Resolution Models in Xilinx Zynq MPSoC ZCU102
  ☆16Updated 5 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆14Updated 8 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆12Updated 4 years ago