dimdano / gan-hlsLinks
Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs
☆11Updated 4 years ago
Alternatives and similar repositories for gan-hls
Users that are interested in gan-hls are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆17Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 5 years ago
- ☆26Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21Updated last year
- 2020 xilinx summer school☆19Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆60Updated 4 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- ☆20Updated 3 years ago
- RTL code for the DPU chip designed for irregular graphs☆13Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆35Updated 6 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆18Updated 3 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- ☆33Updated 4 years ago
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆10Updated 3 years ago
- ☆21Updated 3 years ago
- ☆64Updated 5 years ago
- ☆11Updated last year
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Updated 4 years ago