ultraembedded / riscv_sbcLinks
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
☆30Updated 5 years ago
Alternatives and similar repositories for riscv_sbc
Users that are interested in riscv_sbc are comparing it to the libraries listed below
Sorting:
- IP submodules, formatted for easier CI integration☆30Updated last month
- USB capture IP☆22Updated 5 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆25Updated 3 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- VexRiscV system with GDB-Server in Hardware☆21Updated 2 years ago
- understanding the tinyfpga bootloader☆25Updated 7 years ago
- Small footprint and configurable Inter-Chip communication cores☆65Updated last week
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Repository and Wiki for Chip Hack events.☆52Updated 4 years ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆27Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- PCIe analyzer experiments☆62Updated 5 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- AGM bitstream utilities and decoded files from Supra☆44Updated 2 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆90Updated 11 months ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Updated 5 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- FLIX-V: FPGA, Linux and RISC-V☆41Updated last year
- WCH CH569 SerDes Reverse Engineering☆27Updated 3 years ago
- High Speed USB 2.0 capture device based on miniSpartan6+☆59Updated 5 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆19Updated last year
- JTAG reverse engineering software for FTDI compatible cables☆53Updated 11 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆31Updated 3 years ago