ysalpha / DeepWaterLinks
Neural Network Accelerator Simulator
☆12Updated 9 years ago
Alternatives and similar repositories for DeepWater
Users that are interested in DeepWater are comparing it to the libraries listed below
Sorting:
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13Updated 9 years ago
- ☆36Updated 4 years ago
- ☆38Updated 7 months ago
- ☆29Updated 8 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- ☆15Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- ☆27Updated 6 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 11 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 10 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Updated 3 years ago
- A scalable Eyeriss model in SystemC.☆30Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆54Updated 8 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 8 months ago