riscv-boom / boom-attacksLinks
Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
☆64Updated 5 years ago
Alternatives and similar repositories for boom-attacks
Users that are interested in boom-attacks are comparing it to the libraries listed below
Sorting:
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 4 years ago
- A wrapper for the SPEC CPU2006 benchmark suite.☆88Updated 4 years ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆108Updated 3 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆53Updated 4 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆69Updated 4 months ago
- ☆25Updated 2 years ago
- Documentation for RISC-V Spike☆102Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆71Updated last month
- ☆63Updated 2 months ago
- RISC-V Torture Test☆195Updated last year
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆136Updated last year
- ☆89Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆159Updated 5 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆18Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆135Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆55Updated 3 weeks ago
- RISC-V architecture concurrency model litmus tests☆82Updated 2 months ago
- ☆35Updated 4 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆25Updated last month
- Comment on the rocket-chip source code☆180Updated 6 years ago
- ☆81Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆101Updated this week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- ☆182Updated last year
- Run rocket-chip on FPGA☆70Updated 8 months ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆131Updated 11 months ago