Alternatives and similar repositories for boom-attacks

Users that are interested in boom-attacks are comparing it to the libraries listed below

• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆73Updated this week
• cwfletcher / stt
  ☆35Updated 4 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆112Updated 3 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆55Updated 4 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆106Updated 7 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated 3 weeks ago
• CMU-SAFARI / SoftMC
  SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…
  ☆139Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆27Updated 4 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆90Updated 4 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated last week
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• bring-your-own-core / byoc
  The OpenPiton Platform
  ☆28Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• antmicro / rowhammer-tester
  ☆71Updated 2 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆106Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆92Updated 5 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• ucb-bar / sha3
  ☆81Updated last year