riscv / integrated-matrix-extension
RISC-V Integrated Matrix Development Repository
☆15Updated 7 months ago
Alternatives and similar repositories for integrated-matrix-extension
Users that are interested in integrated-matrix-extension are comparing it to the libraries listed below
Sorting:
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated this week
- ☆30Updated last month
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated last month
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆22Updated 4 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆35Updated 4 months ago
- RISC-V Matrix Specification☆22Updated 5 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆28Updated last month
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- ☆61Updated this week
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Spike with a coherence supported cache model☆13Updated 10 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Administrative repository for the Attached Matrix Facility Task Group☆12Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆25Updated 8 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- Championship Value Prediction (CVP) simulator.☆17Updated 4 years ago
- gem5 FS模式实验手册☆35Updated 2 years ago
- ☆91Updated last year
- ☆27Updated 6 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆15Updated 6 months ago
- ☆11Updated 2 weeks ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ☆28Updated 2 years ago