RISC-V Integrated Matrix Development Repository
☆25Jul 21, 2026Updated this week
Alternatives and similar repositories for integrated-matrix-extension
Users that are interested in integrated-matrix-extension are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Administrative repository for the Integrated Matrix Extension Task Group☆36Apr 25, 2026Updated 3 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆186Apr 1, 2026Updated 3 months ago
- ET Accelerator Firmware and Runtime☆48Jul 17, 2026Updated last week
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated 5 months ago
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆40Mar 6, 2026Updated 4 months ago
- Rocket Chip Generator☆13Jul 31, 2021Updated 4 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆38Mar 26, 2024Updated 2 years ago
- Administrative repository for the Attached Matrix Facility Task Group☆14Dec 11, 2023Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆153Jul 14, 2026Updated last week
- This is the fork of CVA6 intended for PULP development.☆23Jul 16, 2026Updated last week
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 9 months ago
- XuanTie vendor extension Instruction Set spec☆45Jul 3, 2026Updated 3 weeks ago
- Processor support packages☆22Feb 2, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- GCC for Xuantie RISC-V CPU, the GNU Compiler Collection.☆21Apr 12, 2025Updated last year
- TerosHDL documentation☆13Jul 27, 2025Updated 11 months ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- The ISA specification for the Zalasr extension.☆15Mar 6, 2026Updated 4 months ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆65Jun 22, 2026Updated last month
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆45Updated this week
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆14Sep 18, 2024Updated last year
- ☆19Jul 26, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆154Jul 9, 2026Updated 2 weeks ago
- Instruction and files for porting Arm DesignStart to CW305.☆17Dec 6, 2023Updated 2 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- ☆36May 21, 2026Updated 2 months ago
- ☆14Jan 4, 2023Updated 3 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆15Sep 9, 2022Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆34May 22, 2026Updated 2 months ago
- ☆19Updated this week
- This Ubuntu Docker container offers a full desktop experience (XFCE) by using the tightvncserver to provide a VNC connection to the conta…☆17Jun 14, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- Repo for CHERIoT-SAFE development FPGA platform☆21May 28, 2026Updated last month
- ☆15Dec 1, 2022Updated 3 years ago
- HDMI core in Chisel HDL☆54Mar 8, 2024Updated 2 years ago
- sgbm ros with cuda☆12Jun 23, 2018Updated 8 years ago
- The artifact for NDSS '25 paper "ASGARD: Protecting On-Device Deep Neural Networks with Virtualization-Based Trusted Execution Environmen…☆16Oct 16, 2025Updated 9 months ago