sunyata000 / PODES-M0OView external linksLinks
A VerilogHDL MCU Core based ARMv6 Cortex-M0
☆22Jan 31, 2020Updated 6 years ago
Alternatives and similar repositories for PODES-M0O
Users that are interested in PODES-M0O are comparing it to the libraries listed below
Sorting:
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 9 months ago
- ☆11Jun 28, 2020Updated 5 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Mar 21, 2020Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- ☆74Jan 19, 2016Updated 10 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- RISC-V Rocket on the Digilent Zybo Board☆21Aug 6, 2014Updated 11 years ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- An CAN bus Controller implemented in Verilog☆50May 28, 2015Updated 10 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- Interface Protocol in Verilog☆51Aug 2, 2019Updated 6 years ago
- Verilog Implementation of Run Length Encoding for RGB Image Compression☆27Jun 28, 2021Updated 4 years ago
- ☆33Nov 24, 2025Updated 2 months ago
- Implementation of Sobel Filter in Verilog☆25Mar 10, 2017Updated 8 years ago
- ☆24Apr 18, 2021Updated 4 years ago
- STM32F407 + Spartan6 combo with high speed USB TMC interface☆30Apr 20, 2020Updated 5 years ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 13 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 2 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆13Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago