Alternatives and similar repositories for PODES-M0O

Users that are interested in PODES-M0O are comparing it to the libraries listed below

• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• sunyata000 / AMY_MCU
  A MCU implementation based PODES-M0O
  ☆19Updated 5 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆70Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 11 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆36Updated 8 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 6 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆50Updated 3 months ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆71Updated 8 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆80Updated last year
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆24Updated 3 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆94Updated last year
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆60Updated last year
• freecores / i2c
  I2C controller core
  ☆46Updated 2 years ago