Verilog Implementation of Run Length Encoding for RGB Image Compression
☆28Jun 28, 2021Updated 5 years ago
Alternatives and similar repositories for verilog-rle
Users that are interested in verilog-rle are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LZW Compressoion algorithm in verilog☆16Dec 19, 2013Updated 12 years ago
- hardware implement of huffman coding(written in verilog)☆15Jul 30, 2017Updated 9 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆20Feb 13, 2020Updated 6 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆16Jan 3, 2022Updated 4 years ago
- J-core SOC for ice40 FPGA☆20Dec 8, 2019Updated 6 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 9 years ago
- Uart transport + image processing + VGA display 基于FPGA的图像处理，包括Uart和VGA☆22Mar 10, 2020Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- Download YouTube videos and audio with ease (support playlists). Easy to use GUI for yt-dlp written in Qt C++.☆11Feb 6, 2025Updated last year
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆18Jul 11, 2015Updated 11 years ago
- A VHDL implementation of 128 bit AES encryption with a PCIe interface.☆27Jan 9, 2017Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- I2C Master Verilog module☆38Jun 1, 2025Updated last year
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Implementation of Sobel Filter in Verilog☆30Mar 10, 2017Updated 9 years ago
- Erlang version of Ian Bell's "text Elite" (see link below). Also contains an updated version of the original C code.☆13May 29, 2021Updated 5 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler☆10Mar 31, 2018Updated 8 years ago
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆10Sep 30, 2020Updated 6 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆31Dec 1, 2016Updated 9 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆12Oct 20, 2020Updated 6 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆17Feb 18, 2022Updated 4 years ago
- Premium Markets is an automated stock markets technical analysis system. It implements a graphical environment for monitoring and tailori…☆13Jun 27, 2025Updated last year
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated 2 months ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Jan 6, 2020Updated 6 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 6 years ago
- UART 16550 core☆45Jul 17, 2014Updated 12 years ago
- This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projec…☆13Jul 12, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Generate Synthetic Benchmarks for FPGA Research☆10Aug 16, 2022Updated 4 years ago
- Electronic control of microscope elements (camera/laser triggering, TTL, PWM, servos, analog i/o) based on affordable FPGAs, integrated w…☆26Feb 27, 2023Updated 3 years ago
- Video compression systems☆24Jul 17, 2014Updated 12 years ago
- ☆43Apr 28, 2019Updated 7 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 8 years ago
- A set of scripts to build a (somewhat) working Debian image for RISC-V.☆34Aug 30, 2023Updated 3 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago