geraked / verilog-rleLinks
Verilog Implementation of Run Length Encoding for RGB Image Compression
☆27Updated 4 years ago
Alternatives and similar repositories for verilog-rle
Users that are interested in verilog-rle are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆63Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆91Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆75Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆81Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- UART 16550 core☆37Updated 11 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆32Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆68Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 9 months ago
- USB -> AXI Debug Bridge☆40Updated 4 years ago
- TCP/IP controlled VPI JTAG Interface.☆68Updated 9 months ago
- Verilog SPI master and slave☆61Updated 9 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆41Updated last month
- DDR3 SDRAM controller☆18Updated 11 years ago
- ☆74Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- UART models for cocotb☆31Updated 2 months ago