An CAN bus Controller implemented in Verilog
☆52May 28, 2015Updated 10 years ago
Alternatives and similar repositories for CAN-Bus-Controller
Users that are interested in CAN-Bus-Controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CAN Protocol Controller☆41Jul 17, 2014Updated 11 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- The ZipCPU blog☆18Dec 17, 2025Updated 3 months ago
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 11 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Simulation of BLDC control algorithms☆11Jan 4, 2022Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆85Oct 2, 2019Updated 6 years ago
- ☆13Aug 22, 2023Updated 2 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- MD5 core in verilog☆13May 1, 2012Updated 13 years ago
- RTL modbus rtu slave for FPGA☆14Apr 29, 2022Updated 3 years ago
- Modbus block on FPGA☆14Jul 24, 2020Updated 5 years ago
- canopenOnF28335☆14May 27, 2016Updated 9 years ago
- PulseRain FP51 MCU, with peripherals☆17Mar 20, 2018Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆24Jul 17, 2014Updated 11 years ago
- Misc. FPGA Projects☆15May 27, 2025Updated 9 months ago
- Hamming ECC Encoder and Decoder to protect memories☆35Jan 28, 2025Updated last year
- Xanadu - An IDE of SDCC☆14Mar 21, 2017Updated 9 years ago
- Arduino based ARINC 429 Transmitter☆15Mar 11, 2021Updated 5 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Release of PocketSDR NEO* edition schematics, PCB, and BOM in KICAD 7.0 format.☆13Jun 14, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- GCC toolchain for MSP430☆10Apr 2, 2019Updated 6 years ago
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- A lightweight Controller Area Network (CAN) controller in VHDL☆31Oct 30, 2024Updated last year
- An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。☆338Sep 15, 2023Updated 2 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Guaranteed Compression for Short Strings☆17Sep 6, 2019Updated 6 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆16Jan 4, 2020Updated 6 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 3 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 5 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- GCC 4.9.4/Binutils 2.20/Newlib Source code for Tricore Aurix☆23Feb 18, 2022Updated 4 years ago
- ☆27Apr 28, 2021Updated 4 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago