UESTC-ICSDLab / CortexM0_SoC
电子科技大学示范性微电子学院微嵌课程配套代码
☆10Updated 4 months ago
Related projects: ⓘ
- FPGA实现各种小游戏,学习并快乐着☆57Updated 2 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆120Updated 2 months ago
- 2023集创赛紫光同创杯一等奖项目☆56Updated 8 months ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆46Updated 6 months ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆44Updated 2 years ago
- ☆201Updated 3 years ago
- COMS 超大规模集成电路设计书籍☆14Updated 2 years ago
- NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)☆50Updated 6 months ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆27Updated last month
- 一个单发射五级静态流水CPU,采用龙芯32位精简版指令集,支持异常和中断处理,使用AXI总线接口,已集成TLB模块☆9Updated last year
- ☆108Updated 3 weeks ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆58Updated 2 years ago
- njtech digital design. a fpga digital alarm system with Nexys A7 100T☆37Updated 5 years ago
- 国科大高等数字集成电路分析与设计课程2022fall☆22Updated last year
- ☆50Updated last year
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单 的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆108Updated 5 months ago
- ☆25Updated this week
- ☆29Updated last year
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆20Updated this week
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆126Updated 4 years ago
- ☆57Updated last year
- riscv指令集,单周期以及五级流水线CPU☆16Updated 4 months ago
- ☆42Updated 4 years ago
- NSCSCC 信息整合☆218Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆23Updated last year
- ☆52Updated last month
- 东南大学信息学院计算机组成原理课设--利用Verilog实现CPU和POC的原理仿真 | SEU computer architecture project--CPU & POC simulation with verilogHDL☆14Updated 7 months ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆34Updated 4 years ago
- NJU Virtual Board☆217Updated last month
- FPGA project☆193Updated 2 years ago