Alternatives and similar repositories for or1kmvp

Users that are interested in or1kmvp are comparing it to the libraries listed below

• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆36Updated last week
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 6 months ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆42Updated 3 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆12Updated 2 months ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆34Updated last year
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 6 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆55Updated 3 weeks ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆56Updated 2 years ago
• pulp-platform / axi_llc
  ☆27Updated last month
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆23Updated 6 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆12Updated 6 years ago
• accellera-official / cci
  SystemC Configuration, Control and Inspection (CCI)
  ☆16Updated 10 months ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 11 years ago
• riscveval / Rocket-Chip
  ☆23Updated 7 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆19Updated 11 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆40Updated 3 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆33Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆31Updated 4 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 7 months ago
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆44Updated last year
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• dcblack / SCFTGU_BOOK
  Archives of SystemC from The Ground Up Book Exercises
  ☆30Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆33Updated 3 years ago