Alternatives and similar repositories for or1kmvp

Users that are interested in or1kmvp are comparing it to the libraries listed below

• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆68Updated 3 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆44Updated 4 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆23Updated last year
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆53Updated 10 months ago
• AlSaqr-platform / he-soc
  ☆32Updated last week
• nvdla / qbox
  NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)
  ☆26Updated 7 years ago
• riscv / riscv-test-env
  ☆50Updated last month
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 9 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last week
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆33Updated 11 months ago
• quic / qbox
  Qbox
  ☆67Updated this week
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• Minres / HIFIVE1-VP
  A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS
  ☆14Updated last year
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 10 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆45Updated this week
• slaclab / axi-pcie-core
  ☆24Updated last week
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• b224hisl / rioschip
  ☆32Updated 2 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆25Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆25Updated 6 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• Pufferfish / tlm-of-a-pcie-rootcomplex-systemc
  A transaction level model of a PCI express root complex implemented in systemc
  ☆23Updated 11 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated 11 months ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆49Updated 3 months ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆21Updated 6 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆29Updated 11 months ago