janweinstock / or1kmvpLinks
An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
☆14Updated 6 months ago
Alternatives and similar repositories for or1kmvp
Users that are interested in or1kmvp are comparing it to the libraries listed below
Sorting:
- PCI Express controller model☆67Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- RISC-V Virtual Prototype☆44Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- ☆50Updated 3 weeks ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- RISC-V Nexus Trace TG documentation and reference code☆53Updated 9 months ago
- ☆89Updated last month
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- SystemC Common Practices (SCP)☆31Updated 10 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆38Updated 2 months ago
- NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)☆26Updated 7 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆42Updated this week
- Qbox☆60Updated 2 weeks ago
- ☆32Updated 2 weeks ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated this week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 9 months ago
- RISC-V processor tracing tools and library☆16Updated last year
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆17Updated 12 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆119Updated this week
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆14Updated last year