janweinstock / or1kmvpLinks
An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
☆15Updated 9 months ago
Alternatives and similar repositories for or1kmvp
Users that are interested in or1kmvp are comparing it to the libraries listed below
Sorting:
- PCI Express controller model☆71Updated 3 years ago
- RISC-V Virtual Prototype☆46Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- RISC-V Nexus Trace TG documentation and reference code☆56Updated last year
- ☆32Updated last month
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Qbox☆78Updated 2 weeks ago
- ☆51Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated 3 weeks ago
- SystemC Common Practices (SCP)☆34Updated last month
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 3 weeks ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- ☆33Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆159Updated 7 months ago
- ☆40Updated last year
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated last month
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆14Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- ☆89Updated 4 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago