Alternatives and similar repositories for or1kmvp

Users that are interested in or1kmvp are comparing it to the libraries listed below

• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated this week
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆28Updated 6 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆21Updated last year
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 8 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated last month
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆55Updated 2 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 3 weeks ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆43Updated 3 years ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆12Updated 6 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• pulp-platform / axi_llc
  ☆30Updated 2 months ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆18Updated 8 months ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆16Updated 5 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆57Updated 2 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆34Updated 2 years ago
• riscveval / Rocket-Chip
  ☆23Updated 7 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆27Updated last week
• Minres / HIFIVE1-VP
  A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS
  ☆12Updated last year
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆23Updated 6 years ago
• AlSaqr-platform / he-soc
  ☆31Updated last week
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆21Updated 2 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated 11 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆33Updated last year
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated 2 years ago
• ucb-ucie / ucieanalog
  An open-source UCIe implementation developed at UC Berkeley.
  ☆15Updated 11 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 4 years ago