microsoft / calipers
Criticality-aware Framework for Modeling Computer Performance
☆26Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for calipers
- ☆30Updated 4 months ago
- ☆20Updated 8 months ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated last month
- ☆27Updated last year
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 5 months ago
- A Scala library for Context-Dependent Environments☆46Updated 6 months ago
- How to Build an LLVM Backend, published by Packt☆18Updated last month
- A Rocket-based RISC-V superscalar in-order core☆27Updated 2 weeks ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆76Updated last week
- ☆65Updated this week
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆27Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 4 months ago
- HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs☆27Updated last month
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆52Updated this week
- SYCL Reference Manual☆25Updated 6 months ago
- Bridging polyhedral analysis tools to the MLIR framework☆102Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆50Updated this week
- Linux source code for ISCA 2020 paper "Enhancing and Exploiting Contiguity for Fast Memory Virtualization"☆17Updated 4 years ago
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- outline and links for PLDI 2022 tutorial☆17Updated 2 years ago
- Memory System Microbenchmarks☆61Updated last year
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆19Updated 2 weeks ago
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- Experiments and prototypes associated with IREE or MLIR☆49Updated 3 months ago
- HPC Challenge Benchmark☆48Updated last year
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆16Updated this week
- ☆54Updated 2 weeks ago
- ☆22Updated last year
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- ☆80Updated 3 weeks ago