aifoundry-org / et-platformLinks
ET Accelerator Firmware and Runtime
☆25Updated this week
Alternatives and similar repositories for et-platform
Users that are interested in et-platform are comparing it to the libraries listed below
Sorting:
- CV32E40X Design-Verification environment☆16Updated last year
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 8 months ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- ☆61Updated 4 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 4 months ago
- ☆32Updated this week
- The multi-core cluster of a PULP system.☆109Updated last month
- ☆89Updated last week
- ☆89Updated 3 months ago
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 5 months ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated this week
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆42Updated last year
- Example for running IREE in a bare-metal Arm environment.☆40Updated 4 months ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Updated 3 years ago
- Pulp virtual platform☆24Updated 5 months ago
- Wrappers for open source FPU hardware implementations.☆35Updated 3 weeks ago
- ☆32Updated 2 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 2 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆21Updated last month
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- Simple runtime for Pulp platforms☆49Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆106Updated 4 years ago
- ☆35Updated this week
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated last month
- ☆18Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- ☆17Updated 3 years ago