A-suozhang / dpu_on_zcu102Links
The Guidance For Installing dpu and some other stuff On Xilinx ZCU102
☆15Updated 5 years ago
Alternatives and similar repositories for dpu_on_zcu102
Users that are interested in dpu_on_zcu102 are comparing it to the libraries listed below
Sorting:
- ☆72Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆47Updated last year
- ☆66Updated 3 years ago
- An integrated CGRA design framework☆91Updated 9 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- eyeriss-chisel3☆40Updated 3 years ago
- ☆19Updated 7 months ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 10 months ago
- ☆37Updated 2 months ago
- ☆35Updated 6 years ago
- ☆71Updated 5 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- Library of approximate arithmetic circuits☆61Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆64Updated 5 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated 2 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆39Updated 2 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆74Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- ☆71Updated 7 years ago