Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLSLinks
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆54Updated 7 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- Tutorials on HLS Design☆52Updated 6 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆116Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- A repository for SystemC Learning examples☆73Updated 3 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- PCI Express controller model☆71Updated 3 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆127Updated last week
- ☆72Updated 7 years ago
- Learn systemC with examples☆127Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆70Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- ☆57Updated 6 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- ☆66Updated 3 years ago
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- Algorithmic C Machine Learning Library☆26Updated last week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆78Updated last month
- BlackParrot on Zynq☆47Updated 3 weeks ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 5 years ago
- ☆80Updated 11 years ago