Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLSView external linksLinks
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆54Aug 20, 2018Updated 7 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- Benchmarks for High-Level Synthesis☆10Mar 17, 2023Updated 2 years ago
- ☆14Mar 13, 2023Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Aug 2, 2019Updated 6 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆11May 2, 2022Updated 3 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- C++ library for graph ordering☆15Mar 20, 2020Updated 5 years ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆10Aug 14, 2025Updated 6 months ago
- Absinthe is an optimization framework to fuse and tile stencil codes in one shot☆14Jul 17, 2019Updated 6 years ago
- CHAI and RAJA provide an excellent base on which to build portable codes. CARE expands that functionality, adding new features such as lo…☆31Feb 10, 2026Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Feb 6, 2020Updated 6 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Nov 14, 2021Updated 4 years ago
- a project build the SSD net in pynq-z2☆15Aug 1, 2020Updated 5 years ago
- For CPU experiment☆14Feb 23, 2021Updated 4 years ago
- Double precision raytracer for scientific or engineering applications.☆12May 18, 2024Updated last year
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated last year
- Convert C files into Verilog☆20Jan 27, 2019Updated 7 years ago
- ☆35Mar 1, 2019Updated 6 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆18Dec 11, 2018Updated 7 years ago
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Sep 25, 2024Updated last year
- Deprecated ADI fork ➡️ analogdevicesinc/u-boot☆18Nov 26, 2025Updated 2 months ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆336Jul 9, 2019Updated 6 years ago
- Arduino-compatible Sensors adapter (mezzanine) board hardware design files☆14Nov 2, 2016Updated 9 years ago
- Fast Floating Point Operators for High Level Synthesis☆23Feb 23, 2023Updated 2 years ago
- A Method for efficiently processing SpMV using SIMD and load balancing☆17Apr 4, 2022Updated 3 years ago
- An alternative to Boost.MPI for a user friendly C++ interface for MPI (MPICH).☆19Feb 24, 2018Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107May 5, 2018Updated 7 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆155Jan 23, 2020Updated 6 years ago
- RFSoC2x2 board repo for PYNQ☆17Oct 11, 2022Updated 3 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 4 years ago
- minimal code to access ps DDR from PL☆22Oct 18, 2019Updated 6 years ago
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 8 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Jun 11, 2019Updated 6 years ago
- ☆464Sep 10, 2024Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆39Nov 25, 2019Updated 6 years ago
- ☆16Nov 22, 2022Updated 3 years ago
- A low-level intermediate representation for hardware description languages☆28Jun 28, 2020Updated 5 years ago