This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆54Aug 20, 2018Updated 8 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆14Mar 13, 2023Updated 3 years ago
- Benchmarks for High-Level Synthesis☆11Mar 17, 2023Updated 3 years ago
- a project build the SSD net in pynq-z2☆15Aug 1, 2020Updated 6 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆19Dec 11, 2018Updated 7 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Aug 2, 2019Updated 7 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆158Jan 23, 2020Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆56Feb 6, 2020Updated 6 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 9 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆339Jul 9, 2019Updated 7 years ago
- minimal code to access ps DDR from PL☆23Oct 18, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RFSoC2x2 board repo for PYNQ☆17Oct 11, 2022Updated 3 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆74Jun 11, 2019Updated 7 years ago
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Jul 12, 2018Updated 8 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Jul 21, 2022Updated 4 years ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆779May 26, 2017Updated 9 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 6 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆209Nov 14, 2021Updated 4 years ago
- ☆17Nov 22, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆483Sep 10, 2024Updated 2 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆30Mar 24, 2021Updated 5 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- PYNQ学习资料☆179Nov 28, 2019Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆39Nov 25, 2019Updated 6 years ago
- Zynq Workshop for Beginners☆33May 21, 2015Updated 11 years ago
- MatchLib Connections Toolkit - example designs leveraging Connections☆17Sep 10, 2026Updated 3 weeks ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 7 years ago
- A high-performance hardware accelerator for compression/decompression algorithm library of zlib based on kunpeng processor☆17May 19, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆11Mar 13, 2026Updated 6 months ago
- Codes to implement MobileNet V2 in a FPGA☆32Dec 21, 2020Updated 5 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆30Jul 30, 2026Updated 2 months ago
- ☆15Feb 6, 2021Updated 5 years ago
- ☆818Jul 13, 2026Updated 2 months ago