architecture-research-group / gem5-dpdk-setupLinks
This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.
☆11Updated last year
Alternatives and similar repositories for gem5-dpdk-setup
Users that are interested in gem5-dpdk-setup are comparing it to the libraries listed below
Sorting:
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- A Multiplatform benchmark designed to provide holistic, detailed and close-to-hardware view of memory system performance with family of b…☆43Updated 3 months ago
- This is where gem5 based DRAM cache models live.☆20Updated 2 years ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆63Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- ☆15Updated 3 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆23Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Updated 5 years ago
- ☆14Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- ☆26Updated 2 years ago
- A Cycle-level simulator for M2NDP☆32Updated 5 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- ☆24Updated 5 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆32Updated 3 months ago
- ☆20Updated 4 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 4 months ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆53Updated 3 weeks ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆14Updated 3 years ago
- ☆36Updated 3 weeks ago
- Pin based tool for simulation of rack-scale disaggregated memory systems☆32Updated 10 months ago
- Tutorial Material from the SST Team☆25Updated 5 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Updated 7 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- HW/SW co-designed end-host RPC stack☆20Updated 4 years ago
- PIMeval simulator and PIMbench suite☆44Updated 2 months ago