khoapham / efcadLinks
☆14Updated 5 years ago
Alternatives and similar repositories for efcad
Users that are interested in efcad are comparing it to the libraries listed below
Sorting:
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆11Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆66Updated 2 years ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆43Updated 5 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆24Updated 5 years ago
- Chisel components for FPGA projects☆124Updated last year
- FOS - FPGA Operating System☆70Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Hot & Spicy tool suite☆23Updated 3 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.☆41Updated 5 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆16Updated last year
- ☆15Updated 2 years ago
- Connectal is a framework for software-driven hardware development.☆170Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago