Alternatives and similar repositories for onnc-umbrella:

Users that are interested in onnc-umbrella are comparing it to the libraries listed below

• zeasa / nvdla-compiler
  ☆42Updated 5 years ago
• ONNC / onnc-tutorial
  ☆58Updated 2 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• sifive / block-nvdla-sifive
  ☆42Updated 3 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆132Updated 5 years ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆83Updated last year
• ramachav / Simple-Neural-Network-Accelerator
  Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…
  ☆10Updated 5 years ago
• nvdla / vp
  Virtual Platform for NVDLA
  ☆142Updated 6 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆161Updated 3 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆32Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• Xilinx / SDSoC_Examples
  ☆83Updated 4 years ago
• Twine-Umich / Twine
  ☆10Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• pulp-platform / pulp-nn
  ☆78Updated last year
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated last year
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆55Updated this week
• chenhaoc / cnnhwpe
  ☆64Updated 2 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆227Updated 2 weeks ago
• Xilinx / logicnets
  ☆83Updated 8 months ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• JunningWu / Learning-NVDLA-Notes
  NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…
  ☆226Updated 6 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆67Updated 5 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆149Updated last year
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆210Updated 2 years ago
• Xilinx / finn-base
  Open Source Compiler Framework using ONNX as Frontend and IR
  ☆29Updated 2 years ago