This repository is created for conducting RISC-V 5-day workshops
☆23Jul 29, 2020Updated 6 years ago
Alternatives and similar repositories for riscv_workshop_collaterals
Users that are interested in riscv_workshop_collaterals are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- Repository to store all design and testbench files for Senior Design☆23Apr 16, 2020Updated 6 years ago
- ☆14May 11, 2022Updated 4 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆87Oct 28, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆169Apr 1, 2026Updated 4 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- Understand how TCL scripting automates ASIC synthesis and timing analysis using Yosys & OpenTimer, with CSV/Excel inputs acting as fr…☆19Oct 26, 2025Updated 9 months ago
- ☆41Feb 28, 2022Updated 4 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Tiny Tapeout 06☆19Nov 15, 2025Updated 8 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- An overview of TL-Verilog resources and projects☆89Apr 25, 2026Updated 3 months ago
- I took on a challenge to build 31 mini-projects using Python. These projects included a variety of applications and features, such as a h…☆10Jan 13, 2023Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆24Sep 19, 2023Updated 2 years ago
- Analog and RF blocks on Skywaters 130nm☆11Jul 30, 2022Updated 4 years ago
- ☆10Nov 26, 2018Updated 7 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆17Oct 10, 2020Updated 5 years ago
- Open-source drag-and-drop QR code label & badge designer. Framework-agnostic (React, Vue, Angular, Svelte, Node.js). Export to ZPL, PDF, …☆41Updated this week
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆53Feb 22, 2022Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- This repo contains the PUF and authentication codes for IoT authentication protocol development project☆12Apr 11, 2020Updated 6 years ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆163Jun 1, 2024Updated 2 years ago
- Source code for DABANGG attack.☆10Mar 26, 2022Updated 4 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- STM32WL SOC LoRa / LoRaWAN development board with JTAG debugger and sensors for light, temperature, humidity, pressure, 3-axis digital ma…☆20Sep 26, 2025Updated 10 months ago
- How to download & install qemu a toolchain suitable for building and running freestanding RISC-V C/C++ programs☆61Updated this week
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- Modified AWG based on the Raspberry Pico with slight modifications to an already exisiting project☆20Aug 25, 2023Updated 2 years ago
- ☆25Oct 3, 2025Updated 10 months ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- ☆17Sep 19, 2022Updated 3 years ago