kunalg123 / riscv_workshop_collaterals
This repository is created for conducting RISC-V 5-day workshops
☆22Updated 4 years ago
Alternatives and similar repositories for riscv_workshop_collaterals:
Users that are interested in riscv_workshop_collaterals are comparing it to the libraries listed below
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆75Updated last year
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆85Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆40Updated 3 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- ☆40Updated 3 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- ☆45Updated 2 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆17Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆74Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 3 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆62Updated 3 weeks ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆14Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 10 months ago
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- ☆21Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- An overview of TL-Verilog resources and projects☆78Updated 3 weeks ago