kunalg123 / riscv_workshop_collateralsLinks
This repository is created for conducting RISC-V 5-day workshops
☆22Updated 5 years ago
Alternatives and similar repositories for riscv_workshop_collaterals
Users that are interested in riscv_workshop_collaterals are comparing it to the libraries listed below
Sorting:
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆81Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Updated 10 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆176Updated 4 months ago
- An overview of TL-Verilog resources and projects☆82Updated 3 weeks ago
- Basic RISC-V Test SoC☆166Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆117Updated 5 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆57Updated 4 years ago
- ☆19Updated 3 years ago
- ☆42Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆146Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆132Updated 3 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆71Updated 3 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- FuseSoC standard core library☆151Updated last month
- Fabric generator and CAD tools.☆214Updated 2 weeks ago