antonson-j1 / SHA256-Accelerator-Hardware
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an…
☆23Updated 3 years ago
Alternatives and similar repositories for SHA256-Accelerator-Hardware:
Users that are interested in SHA256-Accelerator-Hardware are comparing it to the libraries listed below
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆55Updated last month
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- ☆31Updated 5 years ago
- SoC Based on ARM Cortex-M3☆30Updated 3 weeks ago
- SRAM☆22Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆26Updated 3 years ago
- Simple single-port AXI memory interface☆41Updated 10 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆10Updated 8 months ago
- round robin arbiter☆72Updated 10 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆54Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆26Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Pure digital components of a UCIe controller☆61Updated 2 weeks ago
- ☆55Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆41Updated 3 years ago
- BlackParrot on Zynq☆38Updated last month
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- ☆50Updated 2 years ago