antonson-j1 / SHA256-Accelerator-Hardware
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an…
☆23Updated 3 years ago
Alternatives and similar repositories for SHA256-Accelerator-Hardware:
Users that are interested in SHA256-Accelerator-Hardware are comparing it to the libraries listed below
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- SoC Based on ARM Cortex-M3☆30Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- Implementing Different Adder Structures in Verilog☆66Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆26Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- round robin arbiter☆73Updated 10 years ago
- ☆32Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Updated 7 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated this week
- Simple single-port AXI memory interface☆41Updated 11 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 4 months ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- my UVM training projects☆33Updated 6 years ago
- Pure digital components of a UCIe controller☆62Updated this week
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆43Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆92Updated last year
- This is the repository for the IEEE version of the book☆58Updated 4 years ago