antonson-j1 / SHA256-Accelerator-HardwareLinks
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an …
☆28Updated 4 years ago
Alternatives and similar repositories for SHA256-Accelerator-Hardware
Users that are interested in SHA256-Accelerator-Hardware are comparing it to the libraries listed below
Sorting:
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆186Updated last year
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆265Updated this week
- Verilog/SystemVerilog Guide☆79Updated 2 years ago
- Network on Chip Implementation written in SytemVerilog☆197Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated 3 weeks ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆101Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆144Updated 6 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 2 months ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆68Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 3 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- RISC-V Verification Interface☆135Updated this week
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- A verilog implementation for Network-on-Chip☆81Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- 2D Systolic Array Multiplier☆24Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago