antonson-j1 / SHA256-Accelerator-HardwareView external linksLinks
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an…
☆28Dec 12, 2021Updated 4 years ago
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