Alternatives and similar repositories for SHA256-Accelerator-Hardware:

Users that are interested in SHA256-Accelerator-Hardware are comparing it to the libraries listed below

• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆25Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 10 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆80Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆64Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 2 weeks ago
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆46Updated 2 months ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆44Updated 3 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 4 months ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated 10 months ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆39Updated 9 months ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆164Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated 2 weeks ago
• chipsalliance / uvm-verilator
  ☆89Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆53Updated 4 years ago
• yathAg / openroad_vsd_7nmContest
  ☆14Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆23Updated last year
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆63Updated 3 months ago
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆13Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆56Updated 4 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆38Updated 3 years ago