This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an…
☆32Dec 12, 2021Updated 4 years ago
Alternatives and similar repositories for SHA256-Accelerator-Hardware
Users that are interested in SHA256-Accelerator-Hardware are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆41Jul 3, 2023Updated 3 years ago
- This is Circuit Solver which can solve any kind of circuit for you. Do check it out!!☆12Nov 20, 2022Updated 3 years ago
- DE10 NANO SHA3-256 Proof of Work Miner☆14Sep 8, 2020Updated 6 years ago
- IEEE Executive project for the year 2021-2022☆13Nov 22, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆35Nov 4, 2024Updated last year
- Implementation of RISC-V RV32I☆35Aug 30, 2022Updated 4 years ago
- Huffman encoder☆10Sep 8, 2013Updated 13 years ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆28Jul 10, 2018Updated 8 years ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆19Dec 16, 2017Updated 8 years ago
- Quick'n'dirty FuseSoC+cocotb example☆20Nov 26, 2024Updated last year
- This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator☆48Feb 2, 2022Updated 4 years ago
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆87Oct 28, 2023Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- ☆17Jul 30, 2021Updated 5 years ago
- ☆15Sep 27, 2022Updated 4 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 9 years ago
- bwt: An ANSI C implementation of the Burrows-Wheeler transformation (BWT)☆18Apr 13, 2026Updated 5 months ago
- Scripts for Digital Design flow control.☆18Oct 30, 2025Updated 11 months ago
- ☆21Oct 29, 2023Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆109Jul 3, 2026Updated 2 months ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 4 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- TinkerCAD Resources for Freshies Orientation 2020☆10Jan 3, 2021Updated 5 years ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 12 years ago
- ☆16Mar 22, 2021Updated 5 years ago
- 电子科技大学示范性微电子学院微嵌课程配套代码☆17Dec 10, 2025Updated 9 months ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆14Apr 18, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Original RISC-V 1.0 implementation. Not supported.☆44Oct 4, 2018Updated 7 years ago
- Source code for DABANGG attack.☆11Mar 26, 2022Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆174Updated this week
- ☆24Dec 3, 2021Updated 4 years ago
- Integer Multiplier Generator for Verilog☆26Jul 4, 2025Updated last year
- FFT algorithm for fpga☆26Aug 17, 2021Updated 5 years ago
- zero-riscy CPU Core☆19Jun 10, 2018Updated 8 years ago