os-fpga / Virtual-FPGA-Lab
This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
☆184Updated 9 months ago
Alternatives and similar repositories for Virtual-FPGA-Lab:
Users that are interested in Virtual-FPGA-Lab are comparing it to the libraries listed below
- Verilog implementation of multi-stage 32-bit RISC-V processor☆97Updated 4 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆125Updated 8 months ago
- ☆319Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆75Updated last year
- An overview of TL-Verilog resources and projects☆78Updated 3 weeks ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆237Updated 8 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆83Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- A Single Cycle Risc-V 32 bit CPU☆42Updated 2 years ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆98Updated 8 months ago
- RISC-V Embedded Processor for Approximate Computing☆124Updated last week
- SystemVerilog Tutorial☆138Updated 3 weeks ago
- A simple RISC V core for teaching☆184Updated 3 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆46Updated 2 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆125Updated 3 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆85Updated last month
- A curated list of awesome resources for HDL design and verification☆146Updated this week
- ☆57Updated 3 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆336Updated this week
- ☆87Updated last year
- RISC-V Verification Interface☆89Updated 2 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- SoC based on VexRiscv and ICE40 UP5K☆156Updated last month
- Open source ISS and logic RISC-V 32 bit project☆50Updated this week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated this week
- 100 Days of RTL☆362Updated 8 months ago
- ☆92Updated last year
- Verilog/SystemVerilog Guide☆61Updated last year