os-fpga / Virtual-FPGA-Lab
This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
☆188Updated 2 weeks ago
Alternatives and similar repositories for Virtual-FPGA-Lab
Users that are interested in Virtual-FPGA-Lab are comparing it to the libraries listed below
Sorting:
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated 2 weeks ago
- RISC-V Embedded Processor for Approximate Computing☆125Updated 3 weeks ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆127Updated 9 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆88Updated 2 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆88Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 4 months ago
- ☆58Updated 3 years ago
- RISC-V microcontroller IP core developed in Verilog☆175Updated last month
- SystemVerilog Tutorial☆142Updated this week
- An overview of TL-Verilog resources and projects☆78Updated last month
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆76Updated last year
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆102Updated 9 months ago
- ☆321Updated 2 years ago
- CORE-V Family of RISC-V Cores☆265Updated 3 months ago
- Communication framework for RTL simulation and emulation.☆285Updated last month
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆325Updated 2 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆43Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆128Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- ☆93Updated last year
- Opensource DDR3 Controller☆323Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆371Updated this week
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- Simple 8-bit UART realization on Verilog HDL.☆102Updated last year
- Verilog/SystemVerilog Guide☆66Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆176Updated 2 weeks ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆90Updated this week
- Physical Design Flow from RTL to GDS using Opensource tools.☆101Updated 4 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆245Updated 9 months ago
- https://caravel-user-project.readthedocs.io☆198Updated 2 months ago