os-fpga / Virtual-FPGA-Lab

Related projects ⓘ

Alternatives and complementary repositories for Virtual-FPGA-Lab

• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆69Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆67Updated 10 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆71Updated 7 months ago
• riscv-steel / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆156Updated 2 weeks ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆54Updated 10 months ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆110Updated 3 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆52Updated last week
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆113Updated 11 months ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆78Updated 10 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆168Updated 9 months ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆100Updated 2 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆145Updated 2 weeks ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆74Updated 4 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆205Updated 3 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆293Updated last year
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆83Updated 3 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆134Updated 2 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆206Updated 8 months ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆139Updated last week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆169Updated 2 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆203Updated this week
• digital-design-hq / Digital-Resources
  ☆53Updated 3 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆89Updated 3 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆93Updated 9 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆135Updated 2 months ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆136Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆122Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆74Updated 2 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆168Updated this week