Alternatives and similar repositories for Virtual-FPGA-Lab

Users that are interested in Virtual-FPGA-Lab are comparing it to the libraries listed below

• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆151Updated 3 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆133Updated 3 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆81Updated 2 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last month
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆97Updated 10 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆166Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆167Updated 6 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆374Updated 11 months ago
• HDLForBeginners / Examples
  ☆116Updated 2 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆475Updated this week
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆79Updated 2 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆154Updated 5 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆113Updated last year
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆73Updated 2 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆159Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆318Updated 11 months ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆120Updated 3 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆375Updated 2 years ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆225Updated 11 months ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆172Updated 4 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆290Updated 7 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆195Updated last month
• phoeniX-Digital-Design / phoeniX
  A Reconfigurable RISC-V Core for Approximate Computing
  ☆129Updated 7 months ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆190Updated last month
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆190Updated last week
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆234Updated last week
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆66Updated last year
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆171Updated last year
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆308Updated 2 weeks ago