os-fpga / GettingStartedWithFPGAsLinks
Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.
☆36Updated 2 years ago
Alternatives and similar repositories for GettingStartedWithFPGAs
Users that are interested in GettingStartedWithFPGAs are comparing it to the libraries listed below
Sorting:
- Raptor end-to-end FPGA Compiler and GUI☆86Updated 10 months ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆225Updated 4 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆81Updated 2 years ago
- An overview of TL-Verilog resources and projects☆81Updated 7 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆95Updated 8 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆122Updated 3 months ago
- ☆62Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆108Updated 2 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- Solving Sudokus using open source formal verification tools☆18Updated 3 years ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆74Updated 3 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆97Updated 4 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆84Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆161Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- ☆41Updated last year
- Universal Memory Interface (UMI)☆153Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆100Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆122Updated last month
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago