Domipheus / RPU
Basic RISC-V CPU implementation in VHDL.
☆165Updated 4 years ago
Alternatives and similar repositories for RPU:
Users that are interested in RPU are comparing it to the libraries listed below
- A simple RISC-V processor for use in FPGA designs.☆267Updated 6 months ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆145Updated 8 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- RISC-V CPU Core☆311Updated 8 months ago
- A utility for Composing FPGA designs from Peripherals☆170Updated last month
- Example LED blinking project for your FPGA dev board of choice☆170Updated 2 months ago
- Small footprint and configurable DRAM core☆390Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆306Updated 2 months ago
- FuseSoC standard core library☆126Updated 3 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 10 months ago
- Multi-platform nightly builds of open source FPGA tools☆294Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- A Video display simulator☆161Updated 7 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆317Updated 3 years ago
- A simple, basic, formally verified UART controller☆288Updated last year
- A 32-bit RISC-V soft processor☆309Updated this week
- ☆225Updated 2 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆148Updated 6 years ago
- RISC-V 32-bit microcontroller developed in Verilog☆167Updated 4 months ago
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated this week
- VeeR EL2 Core☆263Updated this week
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆231Updated last week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆362Updated last year
- Yet Another RISC-V Implementation☆86Updated 5 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆93Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆243Updated 3 months ago
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 10 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 2 years ago