Domipheus / RPULinks
Basic RISC-V CPU implementation in VHDL.
☆167Updated 4 years ago
Alternatives and similar repositories for RPU
Users that are interested in RPU are comparing it to the libraries listed below
Sorting:
- A simple RISC-V processor for use in FPGA designs.☆277Updated 10 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆122Updated 4 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆238Updated last month
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆148Updated 8 years ago
- A utility for Composing FPGA designs from Peripherals☆181Updated 6 months ago
- A 32-bit RISC-V soft processor☆311Updated 4 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- A Video display simulator☆171Updated last month
- FuseSoC standard core library☆144Updated last month
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- RISC-V CPU Core☆351Updated 3 weeks ago
- An Open Source configuration of the Arty platform☆130Updated last year
- 😎 A curated list of awesome RISC-V implementations☆137Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- A simple, basic, formally verified UART controller☆306Updated last year
- Small footprint and configurable DRAM core☆426Updated last week
- ☆239Updated 2 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- Example LED blinking project for your FPGA dev board of choice☆178Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆240Updated 8 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Multi-platform nightly builds of open source FPGA tools☆297Updated 3 years ago
- RISC-V microcontroller IP core developed in Verilog☆174Updated 3 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆181Updated 3 weeks ago
- Verilog implementation of a RISC-V core☆121Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆290Updated last week
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆413Updated 2 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 7 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆90Updated 4 months ago