Alternatives and similar repositories for RPU

Users that are interested in RPU are comparing it to the libraries listed below

• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 10 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 7 months ago
• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆150Updated 9 years ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆241Updated 5 months ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆155Updated 7 years ago
• ZipCPU / vgasim
  A Video display simulator
  ☆174Updated 5 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆123Updated 5 years ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated 3 months ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆326Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆389Updated 4 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 6 years ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆184Updated last week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆311Updated last year
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆80Updated 6 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆277Updated 2 weeks ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆411Updated last month
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆133Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆245Updated 2 years ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆98Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated 3 weeks ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆117Updated 4 years ago
• olofk / corescore
  CoreScore
  ☆166Updated this week