Alternatives and similar repositories for RPU

Users that are interested in RPU are comparing it to the libraries listed below

• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆148Updated 8 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆337Updated 2 weeks ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 6 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆237Updated 7 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆118Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆143Updated 3 weeks ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆311Updated 4 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆98Updated 3 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆325Updated 3 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆87Updated 5 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆258Updated 2 months ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆153Updated 7 years ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆174Updated 2 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆118Updated 6 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆158Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆238Updated last month
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆370Updated last year
• ZipCPU / vgasim
  A Video display simulator
  ☆170Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆238Updated 2 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆137Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆288Updated 2 weeks ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆94Updated 9 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆190Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆304Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 7 months ago