Domipheus / RPULinks
Basic RISC-V CPU implementation in VHDL.
☆168Updated 4 years ago
Alternatives and similar repositories for RPU
Users that are interested in RPU are comparing it to the libraries listed below
Sorting:
- A simple RISC-V processor for use in FPGA designs.☆278Updated 11 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆121Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆182Updated 7 months ago
- A 32-bit RISC-V soft processor☆312Updated 2 weeks ago
- A Video display simulator☆171Updated 2 months ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆148Updated 9 years ago
- A simple, basic, formally verified UART controller☆308Updated last year
- 😎 A curated list of awesome RISC-V implementations☆137Updated 2 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆240Updated 2 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆241Updated 9 months ago
- RISC-V CPU Core☆363Updated last month
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- Example LED blinking project for your FPGA dev board of choice☆179Updated 2 months ago
- FuseSoC standard core library☆146Updated 2 months ago
- An Open Source configuration of the Arty platform☆130Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- A FPGA core for a simple SDRAM controller.☆119Updated 3 years ago
- Verilog implementation of a RISC-V core☆122Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Small footprint and configurable DRAM core☆431Updated last month
- RISC-V microcontroller IP core developed in Verilog☆176Updated 3 months ago
- CoreScore☆159Updated 6 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆327Updated 3 years ago
- ☆240Updated 2 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆114Updated 4 years ago