Basic RISC-V CPU implementation in VHDL.
☆172Sep 13, 2020Updated 5 years ago
Alternatives and similar repositories for RPU
Users that are interested in RPU are comparing it to the libraries listed below
Sorting:
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 4 months ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Oct 5, 2020Updated 5 years ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆19Jul 4, 2025Updated 8 months ago
- ☆16Jan 12, 2021Updated 5 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆150Jul 31, 2016Updated 9 years ago
- Xbox demo from 2003☆12Oct 1, 2013Updated 12 years ago
- Source for the PlayStation 2 demo "4 Edges" by The Black Lotus☆11Jul 23, 2016Updated 9 years ago
- Flat Shade Society - Solskogen 2019 invite☆10Oct 2, 2019Updated 6 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Oct 24, 2023Updated 2 years ago
- "Okiedokie" by Soopadoopa☆15Aug 22, 2020Updated 5 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆24Aug 24, 2024Updated last year
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,993Updated this week
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆684Jul 16, 2025Updated 7 months ago
- ☆13Jan 4, 2019Updated 7 years ago
- SERV - The SErial RISC-V CPU☆1,757Feb 19, 2026Updated last week
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆38Jan 11, 2023Updated 3 years ago
- A simple RISC-V processor for use in FPGA designs.☆283Aug 19, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- RISC-V soft core running on Colorlight 5B-74B.☆40Feb 14, 2021Updated 5 years ago
- RISC-V CPU Core☆411Jun 24, 2025Updated 8 months ago
- App to find restaurants around and write reviews☆16Feb 12, 2019Updated 7 years ago
- Amoeba by Excess☆18Jun 7, 2022Updated 3 years ago
- The winning Assembly Summer 2015 4k intro by Prismbeings.☆22Jun 29, 2016Updated 9 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- A 32-bit RISC-V soft processor☆321Jan 26, 2026Updated last month
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Aug 24, 2024Updated last year
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆79Oct 1, 2022Updated 3 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆125Oct 13, 2020Updated 5 years ago
- ☆12May 29, 2020Updated 5 years ago
- ☆11Nov 19, 2019Updated 6 years ago
- 🇲🇺 A list of cool open-source projects made in Mauritius☆12Oct 26, 2023Updated 2 years ago
- Ninjadev's new school demo "Construct" for Solskogen 2019☆13Jul 14, 2019Updated 6 years ago
- Progression of fuel prices in Mauritius (2002 - Present)☆12Apr 28, 2024Updated last year
- ☆11Nov 19, 2019Updated 6 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated 3 weeks ago
- 1k by ferris and decypher☆11Jul 22, 2020Updated 5 years ago