Alternatives and similar repositories for gpu3d

Users that are interested in gpu3d are comparing it to the libraries listed below

• AlSaqr-platform / he-soc
  ☆32Updated last week
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆71Updated 3 weeks ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆19Updated 8 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago
• TinyTapeout / tt-support-tools
  Tiny Tapeout project build tools + chip integration scripts
  ☆28Updated this week
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆36Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆40Updated last week
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated 2 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated last week
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated last year
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆27Updated last week
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆27Updated 4 months ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• riscv-software-src / riscv-isac
  ☆33Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆43Updated 10 months ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• srimanthtenneti / SOC-Design-ARM-M0
  This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
  ☆12Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆109Updated this week
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆34Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 2 months ago