Alternatives and similar repositories for gpu3d

Users that are interested in gpu3d are comparing it to the libraries listed below

• AlSaqr-platform / he-soc
  ☆32Updated last week
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆19Updated 10 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆39Updated 7 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆31Updated 4 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆56Updated last week
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆56Updated 2 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆80Updated 2 months ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 3 months ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆34Updated last year
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆28Updated 3 weeks ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆15Updated 8 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• freecores / tiny_aes
  AES
  ☆15Updated 3 years ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 2 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆53Updated last year