RTimothyEdwards / XCircuit
XCircuit circuit drawing and schematic capture tool
☆111Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for XCircuit
- This repository contain source code for ngspice and ghdl integration☆29Updated last year
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆335Updated this week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆109Updated last week
- ADMS is a code generator for the Verilog-AMS language☆93Updated last year
- Qrouter detail router for digital ASIC designs☆56Updated last month
- Open-source version of SLiCAP, implemented in python☆35Updated 2 months ago
- Coriolis VLSI EDA Tool (LIP6)☆55Updated this week
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆70Updated 5 years ago
- mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice☆187Updated this week
- ☆36Updated last month
- ☆125Updated 5 months ago
- The Xyce™ Parallel Electronic Simulator☆9Updated 3 weeks ago
- ☆107Updated 3 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆58Updated 3 weeks ago
- XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.☆145Updated last week
- IRSIM switch-level simulator for digital circuits☆30Updated 6 months ago
- An innovative Verilog-A compiler☆130Updated 3 months ago
- Skill language interpreter☆58Updated 4 years ago
- Circuit Automatic Characterization Engine☆45Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆194Updated 3 weeks ago
- A tiny Python package to parse spice raw data files.☆43Updated last year
- Language server based on ghdl☆91Updated 11 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆141Updated 5 months ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆41Updated last year
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆212Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆95Updated this week
- ☆107Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆73Updated 3 months ago
- FastHenry is the premium inductance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastHen…☆55Updated 4 years ago
- BAG framework☆41Updated 4 months ago