Alternatives and similar repositories for XCircuit:

Users that are interested in XCircuit are comparing it to the libraries listed below

• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆114Updated 2 weeks ago
• StefanSchippers / xschem
  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…
  ☆366Updated this week
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 5 months ago
• Qucs / ADMS
  ADMS is a code generator for the Verilog-AMS language
  ☆97Updated 2 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆62Updated last month
• rubund / graywolf
  ☆110Updated 4 years ago
• imr / ngspice
  mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice
  ☆199Updated last week
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆76Updated 3 months ago
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆35Updated 3 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆60Updated this week
• Xyce / Xyce
  The Xyce™ Parallel Electronic Simulator
  ☆36Updated 2 weeks ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 10 months ago
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆30Updated 2 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆100Updated last month
• ngspice / ngspice
  ☆152Updated 9 months ago
• google / sky90fd-pdk
  ☆109Updated last year
• efabless / mpw_precheck
  ☆37Updated 3 weeks ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆37Updated this week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆205Updated 4 months ago
• efabless / chipignite-resources
  ☆79Updated 2 years ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆39Updated last year
• pieter3d / simview
  ☆77Updated last year
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆42Updated 8 months ago
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆23Updated 4 years ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆47Updated last month
• bluecheetah / bag
  BAG framework
  ☆40Updated 7 months ago
• wrcad / xictools
  XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
  ☆156Updated this week
• efabless / OpenLane
  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …
  ☆147Updated 9 months ago
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆143Updated 7 months ago
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆105Updated this week