Torc: Tools for Open Reconfigurable Computing
☆39Apr 12, 2017Updated 8 years ago
Alternatives and similar repositories for torc
Users that are interested in torc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- ☆114Feb 2, 2021Updated 5 years ago
- ☆16Aug 21, 2019Updated 6 years ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆44Oct 21, 2019Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Zynq PR Management☆13Apr 20, 2016Updated 9 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆18Nov 15, 2019Updated 6 years ago
- Sigmoid Numbers backed by IEEE Floats☆17Jul 8, 2017Updated 8 years ago
- DyRACT Open Source Repository☆16May 4, 2016Updated 9 years ago
- RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.☆43Dec 14, 2019Updated 6 years ago
- Documenting the Xilinx 7-series bit-stream format.☆860Jun 5, 2025Updated 9 months ago
- ☆23Feb 23, 2016Updated 10 years ago
- ☆19Oct 28, 2024Updated last year
- ☆13Feb 13, 2021Updated 5 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆20Mar 1, 2021Updated 5 years ago
- Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx☆89Jun 10, 2015Updated 10 years ago
- ☆25Mar 27, 2020Updated 5 years ago
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,213Mar 18, 2026Updated last week
- The home of the Chisel3 website☆21May 24, 2024Updated last year
- Xilinx Bitstream Format Library. Easily read .bit files from C programs.☆14Nov 16, 2015Updated 10 years ago
- Verilog Plugin for Intellij IDEA☆10Oct 22, 2020Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- Synthesis minecraft redstone schemes from verilog☆18Sep 20, 2018Updated 7 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- VHDL synthesis (based on ghdl)☆356Mar 14, 2026Updated last week
- PCB combining Raspberry Pi Pico and iCE40 FPGA☆31May 8, 2024Updated last year
- Exhaustive 2-input NAND combinations research tool☆17Mar 1, 2018Updated 8 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Oct 27, 2015Updated 10 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆110Feb 12, 2025Updated last year
- ☆13Feb 8, 2021Updated 5 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- MIRROR of https://codeberg.org/catseye/Vinegar : A semi-concatenative language where every operation can fail☆15Nov 3, 2023Updated 2 years ago
- GAIA Processor☆28Mar 21, 2015Updated 11 years ago
- Cross platform, open source IC layout editor☆16Oct 26, 2025Updated 4 months ago
- Lattice iCE40 FPGA experiments - Work in progress☆106Jun 30, 2021Updated 4 years ago