BAG framework
☆44Jul 24, 2024Updated last year
Alternatives and similar repositories for bag
Users that are interested in bag are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- ☆170Dec 4, 2022Updated 3 years ago
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 6 years ago
- BAG framework☆37Dec 27, 2024Updated last year
- MOSIS MPW Test Data and SPICE Models Collections☆42Apr 2, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆57Sep 30, 2023Updated 2 years ago
- Donald Amundson's Python interface to OpenAccess IC design data API☆18Apr 23, 2010Updated 16 years ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆61May 20, 2020Updated 6 years ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆338Oct 22, 2025Updated 7 months ago
- An EDA tool for automatic device sizing using Gm/Id method.☆16Jan 10, 2026Updated 5 months ago
- Interchange formats for chip design.☆39Feb 15, 2026Updated 4 months ago
- Machine Generated Analog IC Layout☆288Apr 24, 2024Updated 2 years ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated last year
- Read Spectre PSF files☆80Dec 12, 2025Updated 6 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Cadence Virtuoso Design Management System☆38Nov 13, 2022Updated 3 years ago
- Cadence Virtuoso Git Integration written in SKILL++☆162Sep 3, 2022Updated 3 years ago
- AIB Generator: Analog hardware compiler for AIB PHY☆39Aug 22, 2020Updated 5 years ago
- Reinforcement learning assisted analog layout design flow.☆37Jul 29, 2024Updated last year
- PSF simulation data c++ library☆29Jan 14, 2024Updated 2 years ago
- Berkeley Analog Generator☆16Apr 3, 2019Updated 7 years ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆474Updated this week
- ☆366Updated this week
- Integrated Circuit Layout☆62Feb 25, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆127May 11, 2023Updated 3 years ago
- genetic and neural net optimization for circuit design☆19Mar 29, 2022Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆37Apr 9, 2026Updated 2 months ago
- ☆21Apr 19, 2024Updated 2 years ago
- 32-bit RISC-V microcontroller☆12Sep 11, 2021Updated 4 years ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆46Dec 5, 2017Updated 8 years ago
- LAYout with Gridded Objects v2☆68Jun 22, 2025Updated 11 months ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Nov 29, 2020Updated 5 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆55Dec 13, 2025Updated 6 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆322Mar 6, 2026Updated 3 months ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆110Aug 21, 2024Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 4 months ago
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆59Mar 13, 2025Updated last year
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆133Updated this week
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆93Dec 18, 2024Updated last year