bluecheetah / bagView external linksLinks
BAG framework
☆41Jul 24, 2024Updated last year
Alternatives and similar repositories for bag
Users that are interested in bag are comparing it to the libraries listed below
Sorting:
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- ☆160Dec 4, 2022Updated 3 years ago
- Donald Amundson's Python interface to OpenAccess IC design data API☆18Apr 23, 2010Updated 15 years ago
- BAG framework☆32Dec 27, 2024Updated last year
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 5 years ago
- MOSIS MPW Test Data and SPICE Models Collections☆39Apr 2, 2020Updated 5 years ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆59May 20, 2020Updated 5 years ago
- ☆56Sep 30, 2023Updated 2 years ago
- Interchange formats for chip design.☆36Feb 3, 2026Updated last week
- Reinforcement learning assisted analog layout design flow.☆33Jul 29, 2024Updated last year
- An EDA tool for automatic device sizing using Gm/Id method.☆14Jan 10, 2026Updated last month
- Cadence Virtuoso Git Integration written in SKILL++☆158Sep 3, 2022Updated 3 years ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆309Oct 22, 2025Updated 3 months ago
- Read Spectre PSF files☆72Dec 12, 2025Updated 2 months ago
- Machine Generated Analog IC Layout☆268Apr 24, 2024Updated last year
- ☆19Apr 19, 2024Updated last year
- PSF simulation data c++ library☆27Jan 14, 2024Updated 2 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated last month
- Cadence Virtuoso Design Management System☆36Nov 13, 2022Updated 3 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆49Dec 13, 2025Updated 2 months ago
- Integrated Circuit Layout☆57Feb 25, 2025Updated 11 months ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Feb 15, 2024Updated last year
- ☆115Feb 2, 2021Updated 5 years ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆441Updated this week
- Qrouter detail router for digital ASIC designs☆57Nov 13, 2025Updated 3 months ago
- ☆17Jul 12, 2024Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated this week
- ☆122May 11, 2023Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆128Feb 3, 2026Updated last week
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆46Dec 5, 2017Updated 8 years ago
- KLayout technology files for ASAP7 FinFET educational process☆24Feb 5, 2023Updated 3 years ago
- Open Analog Design Environment☆25May 19, 2023Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆51Mar 13, 2025Updated 11 months ago
- ☆333Jan 13, 2026Updated last month
- A padring generator for ASICs☆25May 17, 2023Updated 2 years ago
- XCircuit circuit drawing and schematic capture tool☆139Nov 13, 2025Updated 3 months ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆107Aug 21, 2024Updated last year
- 32-bit RISC-V microcontroller☆12Sep 11, 2021Updated 4 years ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated last year