Alternatives and similar repositories for PresentCryptoEngine

Users that are interested in PresentCryptoEngine are comparing it to the libraries listed below

• VLSIDA / puffery
  Tools for PUF analysis
  ☆11Updated 3 years ago
• Praneshss / Modeling_of_APUF_Compositions
  Python Code and Dataset for different PUFs
  ☆18Updated 4 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 8 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆23Updated 7 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆49Updated 5 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 4 years ago
• Tribler / software-based-PUF
  The first open source software-based Physically Unclonable Function (PUF) using off-the-shelf SRAM
  ☆94Updated 2 weeks ago
• SpinalHDL / VexRiscvSocSoftware
  ☆26Updated 3 years ago
• AmeerAbdelhadi / Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
  Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
  ☆23Updated 6 months ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 5 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆18Updated 5 years ago
• aneeshkandi14 / ascon-hw-public
  ☆21Updated 10 months ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆16Updated 5 years ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆78Updated 3 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆19Updated 11 months ago
• coleblackman / TIDENet
  TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…
  ☆17Updated 2 years ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆75Updated 4 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆31Updated last year
• IarveJ / PYNQ_facialRec
  Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.
  ☆11Updated 7 years ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆23Updated 3 years ago
• ZipCPU / arrowzip
  A ZipCPU based demonstration of the MAX1000 FPGA board
  ☆21Updated 4 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆19Updated 4 years ago
• freecores / tiny_aes
  AES
  ☆14Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆23Updated 6 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆18Updated 5 years ago
• kole-huang / picorv32_soc
  picorv32_soc, simulation env, FPGA, boot code, RTOS
  ☆15Updated 6 years ago