Alternatives and similar repositories for DESim:

Users that are interested in DESim are comparing it to the libraries listed below

• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 7 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆86Updated 3 years ago
• efard / DSPHDL
  ☆40Updated 10 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆74Updated this week
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆40Updated this week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆63Updated 2 years ago
• HDLForBeginners / Examples
  ☆84Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated 3 weeks ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆32Updated last month
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆37Updated last year
• CTSRD-CHERI / quartus-install
  Install Intel FPGA 'Quartus Prime' software on remote servers
  ☆54Updated 9 months ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆64Updated 4 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆134Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆108Updated this week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆57Updated last month
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆41Updated last month
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆48Updated this week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆152Updated 9 months ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆157Updated 2 months ago
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆24Updated 5 years ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆28Updated last month
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆57Updated 2 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆42Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆62Updated 9 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆61Updated 2 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆35Updated 3 months ago
• Digilent / Arty-A7
  ☆16Updated 6 months ago