fpgacademy / DESim

Related projects ⓘ

Alternatives and complementary repositories for DESim

• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆40Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆61Updated 3 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 5 months ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆156Updated last week
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆62Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆53Updated 2 weeks ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated last month
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆69Updated last year
• WajahatRiaz / QuadSPI
  RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
  ☆18Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆66Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆30Updated last month
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆40Updated last year
• hypernyan / eth_vlg
  ☆53Updated 2 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆51Updated last year
• ldoolitt / vhd2vl
  ☆121Updated last year
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆85Updated 3 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆68Updated 11 months ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆32Updated 2 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆58Updated last month
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆23Updated 5 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆69Updated 7 months ago
• aignacio / mpsoc_example
  ☆57Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆44Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago