aritramanna / 3-Wide-RISC-V-OOO-RV32-IM-ProcessorLinks
3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
☆17Updated 2 months ago
Alternatives and similar repositories for 3-Wide-RISC-V-OOO-RV32-IM-Processor
Users that are interested in 3-Wide-RISC-V-OOO-RV32-IM-Processor are comparing it to the libraries listed below
Sorting:
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆64Updated 11 months ago
- ☆37Updated 3 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆110Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆90Updated 4 months ago
- ☆13Updated 6 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated this week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆86Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 3 years ago
- ☆106Updated last week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- SystemVerilog Tutorial☆176Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆144Updated last week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆25Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 9 months ago
- ASIC implementation flow infrastructure☆139Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆50Updated 4 years ago
- ☆13Updated last year
- This repo provide an index of VLSI content creators and their materials☆158Updated last year
- A simple DDR3 memory controller☆60Updated 2 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆119Updated 3 years ago
- Making cocotb testbenches that bit easier☆36Updated 2 weeks ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated 2 weeks ago
- RISC-V Nox core☆68Updated 2 months ago
- SystemVerilog frontend for Yosys☆165Updated this week
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆19Updated 8 months ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated last week