3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
☆32Aug 15, 2025Updated last year
Alternatives and similar repositories for 3-Wide-RISC-V-OOO-RV32-IM-Processor
Users that are interested in 3-Wide-RISC-V-OOO-RV32-IM-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Car Diagnostics Software compatible with ELM327 OBD usb device☆11May 10, 2025Updated last year
- Pushing the bf16 multiplication clock frequency to the max on the nominal corner on IHP 130nm 5L node.☆16Mar 29, 2026Updated 7 months ago
- FPGA ringoscillator for random number generation☆12Dec 22, 2025Updated 10 months ago
- An RTL implementation of a SIMT GPU Core☆32Jun 18, 2026Updated 4 months ago
- mWATTBAT: The open source Radar Chip☆12Sep 1, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- bluecore - risc-v cpu☆16Feb 13, 2026Updated 8 months ago
- A 5-stage pipelined, rv32i core with branch prediction and hazard detection☆15Dec 11, 2025Updated 10 months ago
- A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written …☆17Apr 22, 2017Updated 9 years ago
- SystemVerilog file list pruner☆19Oct 19, 2026Updated last week
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆24Aug 10, 2023Updated 3 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated 2 years ago
- GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure☆74Aug 12, 2026Updated 2 months ago
- Modular RISC-V implementation & SoC☆24Oct 21, 2026Updated last week
- VIP for AXI Protocol☆187May 24, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆45Dec 24, 2020Updated 5 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- Testfield: T593☆15Apr 27, 2026Updated 6 months ago
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆46Oct 23, 2026Updated last week
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 2 months ago
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆16Aug 2, 2026Updated 2 months ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago
- ☆28Mar 19, 2021Updated 5 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆158Oct 2, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 8 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32IM☆19Aug 6, 2026Updated 2 months ago
- Implementation of both, sequential and 5-stage pipelined x86 64-bit processor in Verilog, designed to handle data dependencies like load-…☆14Jul 11, 2023Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆294Updated this week
- MD5 in VHDL☆11Jan 4, 2017Updated 9 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆133Jul 9, 2023Updated 3 years ago
- "Algorithms are not arbiters of objective truth and fairness simply because they're math." ― Zoe Quinn☆10Apr 29, 2020Updated 6 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆52Dec 11, 2023Updated 2 years ago
- Advanced Integrated Circuits 2024☆24Nov 16, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆31Jan 31, 2021Updated 5 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆30Feb 19, 2025Updated last year
- Designing Full Chip from IEEE Paper using AI in SKY130☆44Jul 4, 2026Updated 3 months ago
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆28Jan 24, 2026Updated 9 months ago
- Examples of assertions used in SystemVerilog. Made for udemy course by M. Ramdas☆10Sep 25, 2019Updated 7 years ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆21Aug 25, 2026Updated 2 months ago