aritramanna / 3-Wide-RISC-V-OOO-RV32-IM-ProcessorLinks
3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
☆19Updated 4 months ago
Alternatives and similar repositories for 3-Wide-RISC-V-OOO-RV32-IM-Processor
Users that are interested in 3-Wide-RISC-V-OOO-RV32-IM-Processor are comparing it to the libraries listed below
Sorting:
- Curriculum for a university course to teach chip design using open source EDA tools☆129Updated 2 years ago
- SystemVerilog Tutorial☆186Updated last month
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆69Updated 3 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated last year
- ☆114Updated last month
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆99Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆44Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated last month
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 3 months ago
- Home of the open-source EDA course.☆52Updated 6 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆183Updated this week
- RISC-V Nox core☆71Updated 5 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆30Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆95Updated 7 months ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆23Updated 10 months ago
- A demo system for Ibex including debug support and some peripherals☆85Updated 2 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆21Updated 3 weeks ago
- ☆15Updated last year
- SystemVerilog frontend for Yosys☆186Updated this week
- ☆83Updated 11 months ago
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- ☆43Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last week
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆67Updated last month