CMU-SAFARI / SiMRA-DRAMLinks
Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input majority operations and 3) copying one row's content to up 31 rows in real DDR4 DRAM chips. Described in our DSN'24 paper by Yuksel et al. at https://arxiv.org/abs/2405.06081
☆11Updated last year
Alternatives and similar repositories for SiMRA-DRAM
Users that are interested in SiMRA-DRAM are comparing it to the libraries listed below
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 8 months ago
- Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Proc…☆22Updated 4 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆36Updated 2 weeks ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆46Updated 2 months ago
- ☆26Updated last year
- ☆27Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- DASS HLS Compiler☆29Updated last year
- ☆59Updated last month
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆36Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Processing in Memory Emulation☆20Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 2 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆56Updated 3 years ago
- ☆15Updated 2 years ago
- matrix-coprocessor for RISC-V☆17Updated last month
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆22Updated last year
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆50Updated last month