CMU-SAFARI / SiMRA-DRAMLinks
Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input majority operations and 3) copying one row's content to up 31 rows in real DDR4 DRAM chips. Described in our DSN'24 paper by Yuksel et al. at https://arxiv.org/abs/2405.06081
☆11Updated last year
Alternatives and similar repositories for SiMRA-DRAM
Users that are interested in SiMRA-DRAM are comparing it to the libraries listed below
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 5 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 3 weeks ago
- DASS HLS Compiler☆29Updated 2 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆12Updated last year
- Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Proc…☆28Updated 4 months ago
- ☆17Updated 3 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆25Updated 4 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆29Updated 5 years ago
- ☆87Updated last year
- HW accelerator mapping optimization framework for in-memory computing☆25Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last week
- ☆24Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 7 months ago
- CGRA framework with vectorization support.☆42Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆46Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 6 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- ☆14Updated 2 years ago
- ☆17Updated 2 years ago