Alternatives and similar repositories for FreeRTOS-RISCV

Users that are interested in FreeRTOS-RISCV are comparing it to the libraries listed below

• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 7 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 6 years ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆121Updated 2 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆98Updated 3 years ago
• Nuclei-Software / nuclei-sdk
  Nuclei RISC-V Software Development Kit
  ☆138Updated this week
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• riscv / riscv-test-env
  ☆47Updated last month
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 8 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 11 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆79Updated 3 weeks ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 5 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆118Updated 6 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆75Updated last month
• PulseRain / Rattlesnake
  PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
  ☆34Updated 5 years ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆68Updated 2 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 5 months ago
• riscv / riscv-aia
  ☆89Updated 3 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆158Updated 4 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆85Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago