Alternatives and similar repositories for FreeRTOS-RISCV:

Users that are interested in FreeRTOS-RISCV are comparing it to the libraries listed below

• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆119Updated last year
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• riscv / riscv-CMOs
  ☆86Updated 2 years ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 7 years ago
• riscv / riscv-test-env
  ☆46Updated 2 weeks ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆96Updated 3 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆79Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆51Updated 5 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 3 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated 7 months ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆155Updated 4 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆143Updated 10 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 6 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆113Updated 6 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 8 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago