Alternatives and similar repositories for FreeRTOS-RISCV

Users that are interested in FreeRTOS-RISCV are comparing it to the libraries listed below

• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆122Updated 2 years ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 7 years ago
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 6 months ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• Nuclei-Software / nuclei-sdk
  Nuclei RISC-V Software Development Kit
  ☆142Updated 2 weeks ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• riscv / riscv-test-env
  ☆47Updated 2 months ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆99Updated 3 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆73Updated 7 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 2 months ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 6 years ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆68Updated 2 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated 11 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated last month
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆171Updated 9 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 3 years ago
• PulseRain / Rattlesnake
  PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
  ☆34Updated 5 years ago
• riscv / riscv-aia
  ☆89Updated 3 months ago
• systemc / systemc-2.3
  New release of the systemc libraries
  ☆123Updated 13 years ago