Alternatives and similar repositories for freebsd

Users that are interested in freebsd are comparing it to the libraries listed below

• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆20Updated 12 years ago
• riscvarchive / riscv-poky
  Port of the Yocto Project to the RISC-V ISA
  ☆61Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆75Updated 7 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 6 years ago
• apertus-open-source-cinema / alpha-software
  Axiom Alpha prototype software (FPGA, Linux, etc.)
  ☆30Updated 9 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆73Updated 11 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆64Updated 6 years ago
• opencomputeproject / zaius-barreleye-g2
  OpenPOWER / Open Compute Server, based upon POWER9
  ☆32Updated 7 years ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆23Updated 8 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated last year
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• riscvarchive / riscv-clang
  ☆26Updated 6 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆91Updated 2 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆26Updated 5 years ago
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆126Updated 9 years ago
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated last year
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• matt-kimball / toygpu
  A simple GPU on a TinyFPGA BX
  ☆81Updated 7 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆124Updated 9 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• m-labs / milkymist
  SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
  ☆155Updated 11 years ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆71Updated 4 years ago