freebsd-riscv / freebsd
FreeBSD src tree
☆18Updated 4 years ago
Alternatives and similar repositories for freebsd:
Users that are interested in freebsd are comparing it to the libraries listed below
- LatticeMico32 soft processor☆105Updated 10 years ago
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆18Updated 12 years ago
- SoftCPU/SoC engine-V☆54Updated last month
- Port of the Yocto Project to the RISC-V ISA☆62Updated 6 years ago
- Zephyr port to riscv architecture☆24Updated 7 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆124Updated 9 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- 16 bit RISC-V proof of concept☆23Updated 7 months ago
- ☆63Updated 6 years ago
- RISC-V Frontend Server☆63Updated 6 years ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆25Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- Minimal microprocessor☆20Updated 7 years ago
- OpenRISC Tutorials☆41Updated 8 months ago
- A bit-serial CPU☆18Updated 5 years ago
- Moxie-compatible core repository☆46Updated last year
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- The OpenRISC 1000 architectural simulator☆74Updated last week
- The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.☆77Updated 13 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆63Updated 7 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆78Updated 2 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆32Updated 10 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- ☆31Updated 7 years ago
- MRSIC32 ISA documentation and development☆90Updated last year
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year