fractalclone / zephyr-riscvLinks
Zephyr port to riscv architecture
☆24Updated 8 years ago
Alternatives and similar repositories for zephyr-riscv
Users that are interested in zephyr-riscv are comparing it to the libraries listed below
Sorting:
- A port of FreeRTOS for the RISC-V ISA☆76Updated 6 years ago
- ☆63Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- FreeRTOS for RISC-V☆26Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆28Updated 3 years ago
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆104Updated 7 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- RISC-V XBitmanip Extension☆26Updated 6 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- RISC-V Frontend Server☆63Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- ☆32Updated 7 years ago
- Port of the Yocto Project to the RISC-V ISA☆62Updated 6 years ago
- The OpenRISC 1000 architectural simulator☆76Updated 2 months ago
- A time-predictable processor for mixed-criticality systems☆59Updated 8 months ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- AXI PSRAM Controller IP for use with Digilent Nexys 4☆10Updated 3 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆52Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated last month
- open-source SDKs for the SCR1 core☆73Updated 7 months ago
- ☆47Updated 2 months ago