ucam-comparch / clarviLinks
Clarvi simple RISC-V processor for teaching
☆58Updated 8 years ago
Alternatives and similar repositories for clarvi
Users that are interested in clarvi are comparing it to the libraries listed below
Sorting:
- ☆99Updated 2 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- Platform Level Interrupt Controller☆43Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- An Open-Source Design and Verification Environment for RISC-V☆84Updated 4 years ago
- ☆67Updated 4 years ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆113Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Simple single-port AXI memory interface☆46Updated last year
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆120Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated this week
- ☆40Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆91Updated last month
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆64Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 9 months ago