olofk / fusesocotb
Quick'n'dirty FuseSoC+cocotb example
☆18Updated 3 months ago
Alternatives and similar repositories for fusesocotb:
Users that are interested in fusesocotb are comparing it to the libraries listed below
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 4 months ago
- ☆31Updated 2 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- ☆13Updated 3 months ago
- ☆36Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- An open-source HDL register code generator fast enough to run in real time.☆58Updated last week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 6 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago
- ☆40Updated 3 years ago
- UART models for cocotb☆26Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 9 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 2 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆4Updated 4 months ago
- APB UVC ported to Verilator☆11Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Making cocotb testbenches that bit easier☆29Updated this week
- Wishbone interconnect utilities☆39Updated last month
- SystemVerilog Linter based on pyslang☆29Updated 2 months ago
- USB virtual model in C++ for Verilog☆29Updated 5 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆59Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago