olofk / fusesocotbLinks
Quick'n'dirty FuseSoC+cocotb example
☆18Updated 11 months ago
Alternatives and similar repositories for fusesocotb
Users that are interested in fusesocotb are comparing it to the libraries listed below
Sorting:
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated 2 weeks ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- ☆38Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated last week
- ☆43Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated last month
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- RISC-V Nox core☆68Updated 3 months ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆91Updated this week
- Extended and external tests for Verilator testing☆17Updated this week
- LunaPnR is a place and router for integrated circuits☆47Updated 3 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated 2 weeks ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- UART models for cocotb☆31Updated 2 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- UART cocotb module☆11Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 9 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆48Updated 8 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Bitstream relocation and manipulation tool.☆48Updated 2 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆124Updated 2 weeks ago
- SpiceBind – spice inside HDL simulator☆56Updated 4 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week