Alternatives and similar repositories for fusesocotb

Users that are interested in fusesocotb are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• pulp-platform / svase
  ☆32Updated 4 months ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …
  ☆11Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 weeks ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆14Updated last month
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated 2 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• bsg-idea / uw_openroad_free45
  UW reference flow for Free45PDK and The OpenROAD Project
  ☆11Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• wallento / cocotbext-wishbone
  ☆13Updated 5 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆67Updated 8 months ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆46Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• snishizawa / libretto
  Characterizer
  ☆22Updated 2 weeks ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆6Updated last week
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 2 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago