Alternatives and similar repositories for tinytapeout-06

Users that are interested in tinytapeout-06 are comparing it to the libraries listed below

• TinyTapeout / tt07-verilog-template
  Submission template for Tiny Tapeout 7 - Verilog HDL Projects
  ☆19Updated 11 months ago
• TinyTapeout / tt-multiplexer
  ☆16Updated last week
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated last month
• TinyTapeout / tinytapeout-08
  Tiny Tapeout 8
  ☆13Updated 4 months ago
• TinyTapeout / tt-gds-action
  Tiny Tapeout GDS Action (using OpenLane)
  ☆11Updated last month
• TinyTapeout / tt-micropython-firmware
  TinyTapeout demo pcb's RP2040 functionality
  ☆11Updated 2 months ago
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆20Updated last week
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆15Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆13Updated 2 years ago
• robtaylor / amaranth-awesome
  Awesome projects using the Amaranth HDL
  ☆13Updated 3 months ago
• britovski / adder
  Adder in VHDL to test the digital flow using ghdl and GTKwave (front-end) and openlane (back-end). Translated from the original https://g…
  ☆11Updated 3 years ago
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆17Updated 3 years ago
• algofoogle / raybox-zero
  Minimal implementation of Raybox HDL ray caster concept
  ☆24Updated last week
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆100Updated this week
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago
• TinyTapeout / tinytapeout-03
  ☆15Updated last year
• mikeakohn / riscv_fpga
  Implementation of a RISC-V CPU in Verilog.
  ☆14Updated 2 months ago
• PavlenkoG / ECP5_PCIE_Analyzer
  ☆14Updated last year
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆21Updated 5 months ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆47Updated last month
• dominiksalvet / risc63
  Custom 64-bit pipelined RISC processor
  ☆18Updated 10 months ago
• steveicarus / simbus
  Icarus SIMBUS
  ☆18Updated 5 years ago
• TinyTapeout / tt-demo-pcb
  Demo board for TT4 and beyond
  ☆21Updated 2 months ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆70Updated this week
• TinyTapeout / tt10-verilog-template
  Submission template for Tiny Tapeout 10 - Verilog HDL Projects
  ☆19Updated 2 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆91Updated 8 months ago