TinyTapeout / tinytapeout-06

Related projects ⓘ

Alternatives and complementary repositories for tinytapeout-06

• TinyTapeout / tt-multiplexer
  ☆13Updated this week
• stnolting / neorv32-riscof
  ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆25Updated this week
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆16Updated last week
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆30Updated 6 months ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 2 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆66Updated this week
• efabless / mpw_precheck
  ☆36Updated last month
• mattvenn / wokwi-verilog-gds-test
  ☆54Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆73Updated 2 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆67Updated this week
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago
• controlpaths / filterbuilder
  Filter builder tool
  ☆17Updated 2 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆13Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆66Updated this week
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆13Updated last year
• hdl-util / hdmi-demo
  Demo of hdmi on at 720p with VGA-compatible text mode and sound
  ☆24Updated last year
• openXC7 / toolchain-nix
  Nix flake for openXC7
  ☆27Updated this week
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆28Updated 8 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆46Updated this week
• klessydra / T02x
  A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
  ☆23Updated 3 months ago
• chili-chips-ba / openCologne
  Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…
  ☆46Updated 3 weeks ago
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆37Updated 8 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆52Updated 3 weeks ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 6 months ago
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆30Updated 9 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆36Updated last month
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated last year
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆24Updated 4 years ago
• rejunity / tt05-psg-sn76489
  TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instrum…
  ☆53Updated 3 weeks ago
• algofoogle / raybox-zero
  Minimal implementation of Raybox HDL ray caster concept
  ☆23Updated 2 weeks ago