OSCC-Project / AiEDALinks
RTL-to-Vector-to-GDS
☆16Updated 2 weeks ago
Alternatives and similar repositories for AiEDA
Users that are interested in AiEDA are comparing it to the libraries listed below
Sorting:
- ☆60Updated last week
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆14Updated 2 years ago
- ☆12Updated last year
- ☆82Updated last month
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆51Updated 3 months ago
- UCSD Detailed Router☆90Updated 4 years ago
- ☆31Updated 3 years ago
- Bounded-Skew DME v1.3☆14Updated 7 years ago
- ☆18Updated 9 months ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated last year
- ☆77Updated 3 months ago
- Circuit release of the MAGICAL project☆38Updated 5 years ago
- Analog Placement Quality Prediction☆24Updated 2 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆33Updated 5 years ago
- The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design☆68Updated 7 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆77Updated last year
- VLSI EDA Global Router☆75Updated 7 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- ☆86Updated 2 months ago
- ☆25Updated 4 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆43Updated last month
- ☆84Updated last week
- Machine Generated Analog IC Layout☆252Updated last year
- ☆33Updated 4 years ago
- Artificial Netlist Generator☆42Updated last year
- ☆20Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆56Updated 8 months ago