Alternatives and similar repositories for AiEDA

Users that are interested in AiEDA are comparing it to the libraries listed below

• Ravenslofty / librecell
  ☆26Updated 4 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆32Updated 4 years ago
• CODA-Team / AnalogGym
  ☆74Updated 3 months ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆96Updated 5 years ago
• PKU-IDEA / SAGERoute
  SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
  ☆25Updated 2 years ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆40Updated 6 years ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆129Updated 2 years ago
• parallaxsw / OpenSTA
  ☆98Updated this week
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 6 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆60Updated 5 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆80Updated 8 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• ABKGroup / PROBE3.0
  ☆50Updated last year
• IntelLabs / FloorSet
  ☆79Updated last month
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆142Updated 2 years ago
• PKU-IDEA / SymDetect
  Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks
  ☆16Updated 2 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆190Updated 8 months ago
• NVlabs / INSTA
  ☆95Updated 7 months ago
• laiyao1 / AnalogCoder
  ☆123Updated 2 weeks ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆123Updated 5 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆142Updated 2 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆40Updated 6 years ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆59Updated 5 years ago
• pkuzjx / eda-collection
  ☆109Updated 6 years ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆68Updated 7 months ago
• AvestimehrResearchGroup / AICircuit
  The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design
  ☆80Updated last year
• ChrisZonghaoLi / sky130_ldo_rl
  This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
  ☆48Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆32Updated 10 years ago
• NVlabs / Differentiable-Global-Router
  ☆23Updated last year