geziangfinn / easyPlaceLinks
Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
☆43Updated 8 months ago
Alternatives and similar repositories for easyPlace
Users that are interested in easyPlace are comparing it to the libraries listed below
Sorting:
- Artificial Netlist Generator☆39Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆128Updated 3 weeks ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆23Updated 10 months ago
- ☆44Updated last year
- Analog Placement Quality Prediction☆22Updated 2 years ago
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆39Updated last month
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆76Updated 10 months ago
- RePlAce global placement tool☆236Updated 4 years ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆32Updated last month
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆29Updated 3 years ago
- ☆57Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated 10 months ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆22Updated 10 months ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆126Updated 11 months ago
- ☆9Updated 3 years ago
- ☆12Updated last year
- ☆17Updated 10 months ago
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆270Updated 2 months ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆21Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago
- Machine Generated Analog IC Layout☆239Updated last year
- Bounded-Skew DME v1.3☆14Updated 6 years ago
- ☆23Updated 8 months ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆16Updated 3 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆52Updated 6 months ago
- Analog and mixed-signal automatic placer☆11Updated 2 years ago
- ☆16Updated last year
- ☆33Updated 4 years ago