geziangfinn / easyPlaceLinks
Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
☆44Updated 9 months ago
Alternatives and similar repositories for easyPlace
Users that are interested in easyPlace are comparing it to the libraries listed below
Sorting:
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆133Updated last month
- ☆44Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆76Updated 11 months ago
- RePlAce global placement tool☆236Updated 4 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆23Updated 11 months ago
- Artificial Netlist Generator☆39Updated last year
- ☆34Updated 4 years ago
- ☆57Updated 4 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆127Updated last year
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆39Updated 2 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- ☆15Updated 5 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆28Updated 3 years ago
- ☆12Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆28Updated 2 years ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆21Updated 2 years ago
- Analog Placement Quality Prediction☆23Updated 2 years ago
- ☆9Updated 3 years ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago
- Machine Generated Analog IC Layout☆243Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆21Updated 11 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆43Updated last month
- ☆20Updated 6 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆47Updated last month
- Mirror of the Si2 LEF/DEF parser (v5.8)☆16Updated 3 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆275Updated 2 months ago
- VLSI EDA Global Router☆75Updated 7 years ago
- Bounded-Skew DME v1.3☆14Updated 7 years ago