EDDRSoftware / gdsFileParserLinks
This library is a low level parser for the GDSII file format.
☆36Updated 8 years ago
Alternatives and similar repositories for gdsFileParser
Users that are interested in gdsFileParser are comparing it to the libraries listed below
Sorting:
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆124Updated 2 years ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆42Updated 7 years ago
- C++ library and command-line utility for reading GDSII geometry files☆48Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆56Updated 3 years ago
- GDS to ASCII Converter☆21Updated 2 months ago
- ☆93Updated 6 years ago
- Database and Tool Framework for EDA☆117Updated 4 years ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆21Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆177Updated 3 months ago
- Simple and most probably incomplete parser for spectre netlists☆15Updated 8 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- An open multiple patterning framework☆79Updated last year
- This library is a low level parser for the OpenAccess file format.☆15Updated 8 years ago
- A Design Rule Checker with GPU Acceleration☆54Updated 2 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆23Updated last year
- Fork from https://sourceforge.net/projects/gds3d☆68Updated last year
- Open Source Detailed Placement engine☆39Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- ☆25Updated 4 months ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input …☆230Updated last year
- ☆84Updated this week
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆56Updated last week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆122Updated last week
- ☆22Updated 4 years ago
- ☆25Updated 4 years ago
- UCSD Detailed Router☆90Updated 4 years ago
- Mirror of Synopsys's Liberty parser library☆24Updated 7 years ago
- PVconverter is a language translation tool which can convert the commonly used physical verification programming languages to each other.…☆15Updated 3 years ago