Description of Chinese SM3 Hash algorithm with Verilog HDL
☆55Aug 5, 2018Updated 7 years ago
Alternatives and similar repositories for FPGA-SM3-HASH
Users that are interested in FPGA-SM3-HASH are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA implementation of Chinese SM4 encryption algorithm.☆57Mar 11, 2018Updated 8 years ago
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 6 years ago
- opensource crypto IP core☆30Nov 20, 2020Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Mar 6, 2020Updated 6 years ago
- ☆146Oct 3, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- ☆27Mar 25, 2019Updated 7 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆19Sep 16, 2022Updated 3 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆46Jun 13, 2023Updated 2 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog implementation of the SHA-512 hash function.☆45Jan 17, 2026Updated 3 months ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- ☆27Jun 12, 2022Updated 3 years ago
- ☆26Aug 11, 2021Updated 4 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Verilog implementation of the SHA-1 cryptgraphic hash function☆57Apr 3, 2025Updated last year
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆13Nov 26, 2024Updated last year
- Implementation of RSA algorithm on FPGA using Verilog☆28Aug 1, 2018Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- AES加密解密算法的Verilog实现☆71Jan 17, 2016Updated 10 years ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆12Sep 22, 2020Updated 5 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆16Oct 25, 2017Updated 8 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 6 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- True Random Number Generator core implemented in Verilog.☆84Oct 8, 2020Updated 5 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- ☆19Aug 27, 2022Updated 3 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Mar 31, 2026Updated 2 weeks ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 8 years ago
- Verilog implementation of Mersenne Twister PRNG☆31Jun 20, 2018Updated 7 years ago