secworks / trng

Related projects ⓘ

Alternatives and complementary repositories for trng

• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆114Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆146Updated this week
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆85Updated 3 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆35Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆54Updated 2 months ago
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆16Updated 2 years ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆28Updated 3 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆104Updated 5 years ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆39Updated 9 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆37Updated 7 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆60Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆85Updated 2 months ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆68Updated 10 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆81Updated 6 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆138Updated last year
• jens-na / VexRiscv-CCOPI
  Custom Coprocessor Interface for VexRiscv
  ☆10Updated 6 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆81Updated 2 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆90Updated 3 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆21Updated 6 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆78Updated 5 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago