True Random Number Generator core implemented in Verilog.
☆82Oct 8, 2020Updated 5 years ago
Alternatives and similar repositories for trng
Users that are interested in trng are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆24Nov 24, 2017Updated 8 years ago
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆215Nov 26, 2025Updated 3 months ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Verilog implementation of the SHA-1 cryptgraphic hash function☆57Apr 3, 2025Updated 11 months ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆421Dec 29, 2025Updated 2 months ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated 11 months ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆54Aug 5, 2018Updated 7 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆13Nov 28, 2019Updated 6 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Feb 27, 2025Updated last year
- Audio filtering with pyfda and cocotb☆12Sep 24, 2020Updated 5 years ago
- Hardware random number generator for FPGAs☆10May 7, 2015Updated 10 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆16Oct 25, 2017Updated 8 years ago
- Kogge-Stone Adder in Verilog☆16Nov 19, 2021Updated 4 years ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆11Sep 22, 2020Updated 5 years ago
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 5 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 5 years ago
- Cryptographic Key Generation from PUF Data☆23Oct 29, 2019Updated 6 years ago
- TCL scripts for FPGA (Xilinx)☆35Jul 5, 2022Updated 3 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆42Oct 23, 2016Updated 9 years ago
- ☆19Jul 25, 2018Updated 7 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆16Oct 10, 2020Updated 5 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆13Sep 27, 2018Updated 7 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- Platform Level Interrupt Controller☆46May 10, 2024Updated last year
- AXI support for Migen/MiSoC☆28Jun 5, 2025Updated 9 months ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- Testbenches for HDL projects☆22Updated this week
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Jul 23, 2020Updated 5 years ago
- SystemVerilog Logger☆19Sep 30, 2025Updated 5 months ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆57Mar 11, 2018Updated 8 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Dec 4, 2020Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Jun 6, 2020Updated 5 years ago
- A repo of basic Verilog/SystemVerilog modules useful in other circuits.☆21Nov 18, 2017Updated 8 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago