secworks / trngLinks
True Random Number Generator core implemented in Verilog.
☆75Updated 4 years ago
Alternatives and similar repositories for trng
Users that are interested in trng are comparing it to the libraries listed below
Sorting:
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- Verilog based BCH encoder/decoder☆120Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated this week
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆38Updated 5 years ago
- AES hardware engine for Xilinx Zynq platform☆31Updated 3 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆39Updated 8 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆64Updated 8 years ago
- ☆59Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆71Updated 2 weeks ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆74Updated 6 years ago
- AHB3-Lite Interconnect☆89Updated last year
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆22Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- JTAG Test Access Port (TAP)☆34Updated 10 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- I2C controller core☆46Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆55Updated 4 years ago
- round robin arbiter☆74Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆149Updated 3 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆44Updated 5 months ago
- IEEE P1735 decryptor for VHDL☆32Updated 10 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago