ljgibbslf / SM2_core
opensource crypto IP core
☆26Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for SM2_core
- FPGA implementation of Chinese SM4 encryption algorithm.☆46Updated 6 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆45Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆38Updated last year
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆29Updated 6 years ago
- AES加密解密算法的Verilog实现☆60Updated 8 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- ☆20Updated 5 years ago
- Build an open source, extremely simple DMA.☆19Updated 5 years ago
- ☆47Updated 2 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 10 years ago
- Verilog Implementation of SM4 s-box☆19Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- An FPGA-based GZIP (deflate) compressor, which input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压…☆100Updated last year
- 异步FIFO的内部实现☆24Updated 6 years ago
- ☆34Updated 9 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆62Updated 5 months ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago
- ☆12Updated 9 years ago
- NVMe Controller featuring Hardware Acceleration☆76Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- Must-have verilog systemverilog modules☆25Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- round robin arbiter☆68Updated 10 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆42Updated 5 years ago