ljgibbslf / SM2_coreLinks
opensource crypto IP core
☆27Updated 4 years ago
Alternatives and similar repositories for SM2_core
Users that are interested in SM2_core are comparing it to the libraries listed below
Sorting:
- FPGA implementation of Chinese SM4 encryption algorithm.☆55Updated 7 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- AES加密解密算法的Verilog实现☆66Updated 9 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆50Updated 7 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 6 years ago
- ☆76Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆34Updated 10 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆136Updated last year
- Implementation of the PCIe physical layer☆49Updated last month
- NVMe Controller featuring Hardware Acceleration☆92Updated 4 years ago
- Open-Channel Open-Way Flash Controller☆17Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆44Updated 2 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Updated 7 years ago
- ☆23Updated 6 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆96Updated last year
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- Verilog Ethernet Switch (layer 2)☆46Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Verilog based BCH encoder/decoder☆123Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 3 months ago
- ☆64Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- ☆36Updated 3 years ago