native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
☆46Nov 24, 2014Updated 11 years ago
Alternatives and similar repositories for verilog-utils
Users that are interested in verilog-utils are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43May 22, 2020Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆35May 12, 2020Updated 6 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆22Dec 11, 2023Updated 2 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- AMD Xilinx University Program Vivado tutorial☆50Feb 13, 2023Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆930Apr 15, 2026Updated last month
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- Sata 2 Host Controller for FPGA implementation☆18Oct 11, 2017Updated 8 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- TCP Offload Engine☆78Nov 18, 2017Updated 8 years ago
- SERDES-based TDC core for Spartan-6☆19Aug 2, 2012Updated 13 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- verilog modules☆15May 4, 2020Updated 6 years ago
- ☆34Jul 9, 2025Updated 11 months ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated 2 years ago
- ☆27Apr 28, 2021Updated 5 years ago
- ☆80Feb 5, 2022Updated 4 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆55Aug 5, 2018Updated 7 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- Verilog implementation of the SHA-512 hash function.☆46Jan 17, 2026Updated 4 months ago
- ☆14Apr 12, 2018Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Collection of open-source peripherals in Verilog☆186May 3, 2022Updated 4 years ago
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- Verilator open-source SystemVerilog simulator and lint system☆24Updated this week
- Yilong's NetFPGA-10G Repo☆13May 7, 2015Updated 11 years ago
- A small 32-bit implementation of the RISC-V architecture☆33Apr 10, 2026Updated 2 months ago
- Verilog UART☆568Feb 27, 2025Updated last year
- Verilog implementation of the SHA-1 cryptgraphic hash function☆57Apr 3, 2025Updated last year
- Verilog UART☆198Jun 4, 2013Updated 13 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆19Aug 30, 2020Updated 5 years ago
- Linux UIO Driver for AXI DMA☆15Jul 23, 2018Updated 7 years ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- ☆11Sep 14, 2020Updated 5 years ago
- RTL for mipi serialize and deserialize☆11Oct 16, 2017Updated 8 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Dec 17, 2025Updated 5 months ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago