secworks / sha1
Verilog implementation of the SHA-1 cryptgraphic hash function
☆52Updated last month
Alternatives and similar repositories for sha1
Users that are interested in sha1 are comparing it to the libraries listed below
Sorting:
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆44Updated 10 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆38Updated 5 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆39Updated 7 years ago
- round robin arbiter☆73Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog Content Addressable Memory Module☆106Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Altera Advanced Synthesis Cookbook 11.0☆103Updated 2 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆62Updated 8 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆52Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 6 months ago
- Implementation of the SHA256 Algorithm in Verilog☆37Updated 13 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆147Updated 2 months ago
- ☆38Updated last year
- UART 16550 core☆36Updated 10 years ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆26Updated 6 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆74Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆81Updated 5 years ago
- Mathematical Functions in Verilog☆92Updated 4 years ago