secworks / sha1Links
Verilog implementation of the SHA-1 cryptgraphic hash function
☆52Updated 3 months ago
Alternatives and similar repositories for sha1
Users that are interested in sha1 are comparing it to the libraries listed below
Sorting:
- round robin arbiter☆74Updated 11 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆44Updated 10 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- Mathematical Functions in Verilog☆93Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆66Updated 8 months ago
- A simple DDR3 memory controller☆57Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Altera Advanced Synthesis Cookbook 11.0☆104Updated 2 years ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆65Updated 8 years ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 2 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Ethernet 10GE MAC☆45Updated 11 years ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆26Updated 7 years ago
- SystemVerilog Design Patterns☆26Updated 10 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆102Updated last week
- Synthesizable and Parameterized Cache Controller in Verilog☆44Updated 2 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Updated 11 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆39Updated 8 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆56Updated 5 years ago
- Yet Another RISC-V Implementation☆96Updated 9 months ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago