Verilog implementation of the SHA-1 cryptgraphic hash function
☆57Apr 3, 2025Updated 11 months ago
Alternatives and similar repositories for sha1
Users that are interested in sha1 are comparing it to the libraries listed below
Sorting:
- Verilog implementation of the SHA-512 hash function.☆44Jan 17, 2026Updated 2 months ago
- LZW Compressoion algorithm in verilog☆17Dec 19, 2013Updated 12 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆23Feb 20, 2017Updated 9 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Sep 24, 2018Updated 7 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆54Aug 5, 2018Updated 7 years ago
- A Verilog implementation of the popular video game Tetris.☆27Oct 28, 2015Updated 10 years ago
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆81Sep 14, 2023Updated 2 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- ☆13Apr 24, 2015Updated 10 years ago
- SHA3 (KECCAK)☆18Jul 17, 2014Updated 11 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Lab Mouse Security research pertaining to RISC-V☆11May 13, 2017Updated 8 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Nov 24, 2014Updated 11 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- FPGA CryptoNight V7 Minner☆31Aug 26, 2019Updated 6 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Nov 12, 2025Updated 4 months ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- hardware implement of huffman coding(written in verilog)☆14Jul 30, 2017Updated 8 years ago
- ☆26Mar 25, 2019Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- ☆14Jan 24, 2023Updated 3 years ago
- UVM☆13Mar 16, 2020Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- opensource crypto IP core☆30Nov 20, 2020Updated 5 years ago
- Implementation of Sobel Filter in Verilog☆25Mar 10, 2017Updated 9 years ago
- Plugin for CTFd that integrates a web based shell☆14Apr 16, 2018Updated 7 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆28Aug 1, 2018Updated 7 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 10 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago